In this topic we introduce the PIC16F84 MCU, which we will use as our baseline exemplar for the rest of the text. Here we will primarily look at internal structure, reserving external interfacing considerations for Part 3 of the topic.
After reading this topic you should:
• Recognize the difference between a microprocessor and microcontroller.
• Understand the Harvard-based architecture with its parallel fetch and execute units.
• Appreciate the function, structure and memory map of the unrelated Program and Data stores.
• Be able to interpret the Status register bits that control memory paging and hold the C, DC and Z flags.
• Know how to manipulate the contents of the Program Counter in conjunction with the PCLATH special-purpose file register.
• Understand the interaction between the clock phases and the internal sequence of micro-operations.
• Appreciates the principle of banking in the Data store and its relationship to the RP0 control bit in the Status register.
• Know what peripheral functions are integral to the PIC16F84.
What exactly is a microcontroller unit? In a nutshell, a microcontroller is a MicroProcessor Unit (MPU) which is integrated with memory and input/output peripheral interface functions on the (usually) one integrated circuit. In essence it is a MPU with on-board system support circuitry. Thus we begin by investigating the origins of the MPU. From a historical perspective the story begins in 1968 when Robert Noyce (one of the inventors of the integrated circuit), Gordon Moore1 and Andrew Grove left the Fairchild Corporation and founded their own company, which they called Intel.2 Within three years, Intel had developed all the basic types of semiconductor memories used today – dynamic and static RAMs and EPROMs.
As a sideline Intel also designed large-scale integrated circuits to customers’ specifications. In 1970 they were approached by the Nippon Calculating Machine Corporation, and asked to manufacture a suitable chip set for a line of calculators to be named Busicom. At that time calculators were a fast-evolving product and any LSI devices were likely to be superseded within a few years. This of course would reduce an LSI product’s profitability and increase its cost. Engineer Ted Hoff – reputedly while on a topless beach in Tahiti – came up with a revolutionary way to tackle this project. Why not make a simple computer central computing unit (CPU) on silicon? This could then be programmed to implement the calculator functions, and as time progressed these could be enhanced by developing this software. Besides giving the chip a longer and more profitable life, Intel were in the business of making memories – and computer-like architectures need lots of memory. Truly a brain wave. The Japanese company endorsed the Intel design for its simplicity and flexibility in late 1969, rather than the conventional implementation.
Federico Faggin joined Intel in spring 19703 and by the end of the year had produced working samples of the first chip set. This could only be sold to the Nippon Calculating Machine Corporation, but by the middle of 1971, in return for a price reduction, Intel were given the right to sell the chip set to anyone for non-calculator purposes. Intel was dubious about the market for this device, but went ahead and advertised the 4004 "Micro-Programmable Computer on a Chip" in the Electronic News of November 1971. The term microprocessor unit was not coined until 1972. The 4004 created a lot of interest as a means of introducing ‘intelligence’ into electronic products.
The 4004 MPU featured a von Neumann architecture using a four-bit data bus, with direct addressing of 512 bytes of memory. Clocked at 108 kHz, it was implemented with a transistor count of 2300.4 Within a year the eight-bit 200 kHz 8008 appeared, addressing 16 Kbytes and needing a 3500 transistor implementation. Four bits is satisfactory for the BCD digits used in calculators but eight bits is more appropriate for intelligent data terminals (like cash registers) which need to handle a wide range of alphanumeric characters. The 8008 was replaced by the 80805 in 1974, and then the slightly modified 8085 in 1976. The 8085 is still the current Intel eight-bit device. Strangely, 4-bit MPUs were to outsell all other sizes until the early 1990s.
The MPU concept was such a hit that many other electronic manufactures clambered on to the bandwagon. In addition, many designers jumped ship and set up shop on their own, such as Zilog. By 1976 there were 54 different MPUs either available or announced. For example, one of the most successful families was based on the 6800 introduced by Mo-torola.6 The Motorola 6800 had a clean and flexible architecture, could be clocked at 2 MHz and address up to 64 Kbyte of memory. The 6802 (1977) even had 128 bytes of on-board memory and an internal clock oscillator. By 1979 the improved 6809 represented the last in the line of these eight-bit devices, competing mainly with the Intel 8085, Zilog Z80 and MOS Technology’s 6502.
The MPU was not really devised to power conventional computers, but a small calculator company called MITS,7 faced with bankruptcy, took a final desperate gamble in 1975 and decided to make and market a computer. This primitive machine, designed by Ed Roberts, was based on the 8080 MPU and interacted with the operator using front panel toggle switches and lamps – no keyboard and VDU. The Altair8 was advertised for $ 500, and within a month MITS had $2 50,000 in the bank for advance orders.
This first Personal Computer (PC) spawned a generation of computer hackers. Thus an unknown 19-year-old Harvard computer science student, Bill Gates, and a visiting friend, Paul Allen, in December 1975 noticed a picture of the Altair9 on the front cover of Popular Electronics and decided to write software for this primordial PC. They called Ed Robert with a bluff, telling him that they had just about finished a version of the BASIC programming language that would run on the Altair. Thus was the Microsoft Corporation born.
In a parallel development, 22 Altair owners in San Francisco set up the Home-brew club. Two members were Steve Jobs and Steve Wozniak. As a club demonstration, they built a PC which they called the Apple.10 By 1978 the Apple II made $700,000; in 1979 sales were $7 million, and then $48 million.
The Apple II was based around the low-cost 6502 MPU which was produced by a company called MOS Technology. It was designed by Chuck Peddle, who was also responsible for the 6800 MPU, and had subsequently left Motorola. The 6502 bore an uncanny resemblance to the Motorola 6800 family and indeed Motorola sued to prevent the related 6501 MPU being sold, as it even had the same pinout as the 6800. The 6502 was one of the main players in PC hardware by the end of the 1970s, being the computing engine of the BBC series and Commodore PETs amongst many others.
What really powered up Apple II sales was the VisiCalc spreadsheet package. When the business community discovered that the PC was not just a toy, but could do ‘real’ tasks, sales took off. The same thing happened to the IBM PC. Reluctantly introduced by IBM in 1981, the PC was powered by an Intel 8088 MPU clocked at 4.77 MHz together with 128 Kbyte of RAM, a twin 360 Kbyte disk drive and a monochrome text-only VDU. The operating system was Microsoft’s PC/MS-DOS version 1.0. The spreadsheet package here was Lotus 1-2-3.
By the end of the 1970s the technology of silicon VLSI fabrication had progressed to the stage that several tens of thousands transistors could be integrated on the one chip. Microprocessor designers were quick to exploit this capability in one of two ways. The better known of these was to increase the size of the ALU and buses/memory capacity. Intel were the first with the 29,000-transistor 8086, introduced in 1978 as a 16-bit version of the 8085 MPU.11 It was designed to be compatible with its eight-bit predecessor in both hardware and software aspects. This was wise commercially, in order to keep the 8085′s extensive customer base from looking at competitor products, but technically dubious. It was such previous experience that led IBM to use the 8088 version, which had a reduced eight-bit data bus and 20-bit address bus12 to save board space.
In 1979 Motorola brought out its 16-bit offering called the 68000 and its eight-bit data bus version, the 68008 MPU. However, internally it was 32-bit, and this has provided compatibility right up to the 68060 introduced in 1995 and ColdFire RISC device launched in 1997. With a much smaller eight-bit customer base to worry about, the 68000 MPU was an entirely new design and technically much in advance of its 80X86 rivals.
The 68000 was adopted by Apple for its Macintosh series of PCs. However, the Apple Mac only accounts for less than 5% of PC sales. Motorola MPUs have been much more successful in the embedded microprocessor market, the area of smart instrumentation from egg timers to aircraft management systems. Of course, this is just the area which MPUs were developed for in the first place, and the number, if not the profile and value, of devices sold for this purpose exceeds those for computers by more than an order of magnitude.
In this applications area an MPU is ‘buried’ in the application circuit together with memory and various input and output interface circuits. The MPU with its program acts as the controller of the system by virtue of the software in program memory. Over 3.5 billion microprocessor and related devices are sold each year for embedded control, making up over 90% of the MPU market.
The second way of using the additional integrated circuit complexity that became available by the end of the 1970s was to keep a relatively simple CPU and use the extra silicon ‘real estate’ to implement on-board memory and input/output interface. In doing so, simple embedded control systems on the one chip became possible and the overall chip count to implement a given function was thereby considerably reduced. The majority of control tasks require relatively little computing power, but the reduction in size (and therefore cost) is vital. A simple example of this is the intelligent smart card, which has a processor integrated into the card itself. Such microprocessor-based devices were called MicroController Units (MCUs).13 For example there are about 100 microcontrollers hidden in every home; in the washing machine, microwave oven, telephones, electronic games and so on. About 20 more lurk in the average family car.14
Fig. 4.1 An example of a system based on a microcontroller.
In terms of architecture, referring back to Figs. 3.1 and 3.2 and 44 respectively, the microprocessor is the central processor unit, whereas the microcontroller is the complete functioning computer-like system. As an example, consider the electronics of a car odometer monitoring system displaying total distance since manufacture and also a trip odometer. The main system input signal is a tachometer generating pulses on each rotation of the engine flywheel, which when totalized gives the number of engine revolutions – and the pulse to pulse duration could also give the road speed. Of course the actual road distance depends on the gearing of the engine, and thus we need to know which of the five gear ratios has been chosen by the driver at any time. This is shown as five lines G1.. ,G5 originating from the gear box. One signal will be high for the appropriate forward gear, with neutral and reverse being ignored. Additional inputs are used to give a manufacturer’s option of a mile or kilometer display, and a user input to reset the trip display to zero.
The display itself consists of seven 7-segment digits to indicate up to (optimistically) gggggg.g. As there are so many segments to control (49 in total), Fig. 4.1 shows the display data fed via a single digital line, shunted serially into a shift register – see Fig. 2.20. A second line provides clock pulses for the register with 49 clock pulses being needed to refresh the display.15
The trip odometer display comprises four digits, which will record up to ggg.g. Similarly two output lines are used to feed and clock the shift register, and 28 clock pulses are needed to shift in a new 4-digit trip display.
The resource budget (list of subsystem functions) for this system is:
• An edge-triggered input for the tachometer pulse train, connected to a counter/timer to totalize engine revolutions.
• Seven static digital input lines to interface to the gear ratio, mi/km option and trip reset.
• Four output digital lines to clock the two shift registers and provide segment data.
• A microprocessor to do the calculations and to read/write to the input/ output ports respectively.
• Program memory, usually ROM of some kind.
• Data memory for temporary storage of program variables, usually static RAM.
• Non-volatile storage for physical variables, such as total distance and distance since trip reset.
This functionality could be implemented onto a single integrated circuit, and in this situation would be known as a microcontroller, that is a microprocessor integrated with its support circuitry giving a complete microcomputer function. Of course the resource budget listed above is specific to our example. Although the core functions (microprocessor and memory) are common to a wide range of applications, the input/output (I/O) interface needs to be tailored to the task in hand. Some typical I/O functions are:
• I/O to interface to a serial bit stream of various synchronous and asynchronous protocols.
• Counter/timer functions to totalize input events and to generate precision time-varying digital output signals.
• Analog to digital multiplex/conversion to be able to read and digitize analog inputs.
• Digital to analog conversion to output analog signals.
• Display ports to drive multi-digit liquid crystal displays.
This alternative approach to using additional silicon resources led to the first MCUs in the late 1970s. For example the 35,000 transistor Motorola 6801, designed in response to a specific application from an car manufacturer, used the existing 6800 MPU as a core, with 2048 bytes of ROM program memory, 128 bytes of data RAM, 29 I/O lines and a 16bit timer. With the viability of the MCU approach vindicated, a range of families, each based on a specific core but with individual family members having a different selection of I/O facilities, was introduced by the leading MPU manufacturers. For example, the Motorola 68HC11 family (a development of the 6801 MCU) uses a slightly enhanced 6800 core. The 68HC12 and 68HC16 families use 16-bit cores but are designed to be upwardly compatible with the 8-bit 68HC11. It was quickly realised that many embedded applications did not even need the power of the (antique) 6800 core, and the 68HC05 family16 had a severely reduced core by lower price. Actually 4-bit MCUs outsold all other kinds of processor until the early 1990s and 8-bit MCUs, now the most popular, are likely to continue in this role for the foreseeable future.
All these MPUs and MCUs were based on the von Neumann architecture used by mainframe computers. The alternative Harvard architecture,which is chiefly distinguished by having a separate memory space for program and data, originated at Harvard university for a US Defence department computing project, but was rejected in favor of a rival von Neumann design from Princeton university. The first MPU using this architecture was the Sig-netics 8X300, and this was adapted by General Instruments in the mid 1970s for use as a Peripheral Interface Controller (PIC) which was designed to be a programmable I/O port for their 16-bit CP1600 MPU.
General Instruments sold off their microelectronics division in 1988 to a start up company called Arizona Microchip Technology. Microchip’s main product was, and is still, a series of microcontroller families based on this PIC architecture. Their first family was introduced in 1989 with the PIC16C5X series. These Harvard processors are based on a set of only 33 instructions. All instructions are coded in a single 12-bit word. This use of a primordial instruction set is known as Reduced Instruction Set Computer (RISC) and contrasts with the Complex Instruction Set Computer (CISC) model used in most computers/MPUs where several hundred instructions/modes are provided, and because of their number take several memory words to encode. The combination of single-word instructions, the simplified instruction decoder implicit with the RISC paradigm and the Harvard separate Program and Data buses gives a fast, efficient and cost effective processor implementation. The PIC16C5XX 12-bit core family features between 512 and 2048-instruction Program stores implemented as One-Time Programmable (OTP) EEPROM, 25 to 73 bytes of Data memory, 12 or 20 I/O pins in the 18- and 28-pin package respectively, and an 8-bit timer. The PIC12CXXX family are 8-pin equivalents.
By 1992 the PIC16CXXX family family based on a 14-bit core enabled easier addressing of larger Program spaces and additional peripheral devices, such as 16-bit timers and A/D converters as well as interrupt handling. The RISC instruction set is virtually identical to the 12-bit core, with a total of 35 instructions. The 16-bit PIC17CXXX core, introduced in 1997, has 58 instruction, with a multiplying ALU and further interface capabilities. It is complemented by the extended 16-bit core PIC18CXXX family introduced in 1999 with 77 instructions more oriented towards high-level language compiler needs.
Of the three families, the 14-bit core is a good compromise between low-cost and ease of use. The PIC16F84, which is the baseline exemplar of this topic, is a member of this mid-range family.
From the software point of view all devices with the same core are identical. However, there is a different mix of I/O facilities from the hardware perspective, but with much commonalty. For example, the 16C74 supports an 8-channel analog input port, the PIC16C66 a synchronous serial port and the PIC16F84 a non-volatile data memory. All three devices have similar parallel I/O, timer and interrupt handling facilities.
The architecture of the PIC16F84 is shown in a simplified form in Fig. 4.2. Although initially this looks rather complex, it is little more than the architecture of our BASIC computer of Fig. 3.3 but with interface ports connected to the internal File store data bus. You should revise this material now as background to our discussion. In essence the PIC family is based on a Harvard structure with its separate Program and Data store, and with peripheral interface ports mapped onto the Data file store address space. That is the various ports appear to the software to be in the Data store. In more detail we have: Central Processor Unit.
Fig. 4.2 Architecture of the PIC16F84 microcontroller
As a consequence of the Harvard architecture, the CPU is split between the fetch and execution function, both of which operate in parallel with a minimum of interaction.
Fetch
The fetch section comprises a 13-bit Program Counter (PC) addressing the Program store via the Program address bus, and a two-deep Instruction pipeline through which 14-bit instructions via the Program data bus progress through to the Instruction decoder.
The Program Counter is actually located in the Data file store at location File 2 and is labelled as PCL (Program Counter Low byte) in Fig. 4.6.
This means that it can be accessed and manipulated by the software in the same manner as any other file register. For example, if the contents of the Working register were n, then the instruction addwf 2,f overwrites File 2 (i.e. the PC) with its original value plus n – that is skip forward n places. A practical example is given in Program.
There is one problem with this example, which arises because the PC is actually 13-bits wide and File 2 only holds the lower eight bits, PC[7...0]. The upper five bits, PC[12...8] are held in a ‘buried’ register; that is not directly accessible to the programmer. Actually any instruction that directly writes to File 2, such as our example above, does change all 13 PC bits as shown in Fig. 4.3. Not only will the 8-bit outcome of the instruction addwf 2,f be placed in the lower byte of the PC but the lower five bits of the PC buffer register at File 0Ah, labelled PCLATH (for Program Counter LATch High byte) in Fig. 4.3, are automatically copied into the high byte of the Program Counter. The PCLATH file data register is cleared when the PIC is reset and so an instruction like our example will usually result in an address in the first 256-byte.Thus care needs to be taken when altering the state of the PC by writing to PCL in this manner; especially if the outcome overflows its 8-bit field. Instructions that indirectly alter the value of the PC, such as goto, will also use part of the contents of PCLATH in updating the PC. Such instructions carry an 11-bit address as part of the instruction code. Here bits PCLATH[4:3] are moved over to the corresponding PC bits 12 & 11 to give a complete 13-bit PC update.
Associated with the Program Counter is an area of buried storage that can stack up to eight copies of the PC. The current value of the PC is pushed into this stack when a subroutine is called or an interrupt is serviced. Conversely a return from a subroutine or interrupt causes the last stacked PC value to be popped out again into the PC. Details are given in topics 6 and 7.
Fig. 4.3 Showing how all 13 bits of the Program Counter are altered when writing to PCL.
The PIC microcontrollers have an integral oscillator that generates the internal timing sequences. The oscillator frequency fosc is normally controlled by an external crystal (or ceramic)-capacitor network across the device OSC1 and OSC2 pins.A resistor-capacitor connected to OSC1 may be used as the timing elements where lower precision and frequency stability is not an issue. In this case OSC2/CLKOUT outputs a signal of frequency 4 x fosc. Alternatively an external oscillator can be used as the master clock into OSC1/CLKIN. The PIC16F84 has a maximum frequency fOsc of 10 MHz but there is no minimum. As we shall see (Fig. 10.2 )the lower the frequency the smaller is the power consumption. Unless otherwise stated, we will assume a fosc of 4 MHz for the rest of the text.
The internal oscillator/clock circuitry must be configured to the appropriate mode, as described in Fig. 10.5. This is normally done when code is blasted into the Program store flash EEPROM. When the PIC is powered up (external supply voltage is applied) a 72 ms internal reset pulse is generated by the Power-up timer after the supply rises above approximately 2 volts, followed by 1024 clock pulses, counted by the Oscillator Start-Up timer to ensure that the internal oscillator has stabilised. This latter guard timer only operates for crystal-type oscillator modes. The Power-Up timer does not operate if an external reset is applied to the Master CLeaR (MCLR) pin.
Fig. 4.4 Internal clock sequencing waveforms.
The clock input/crystal frequency at the OSC1 pin is divided by four to generate four internal non-overlapping quadrature clocks, as shown in Fig. 4.4. The clock-related sequence of operations in the fetch unit are: Q1: Increment the Program Counter and copy onto the Program store address bus.
Q4: Read the instruction code off the Program store data bus into Instruction register 1 and at the same time move the previous instruction down the pipeline into Instruction register 2, where it is presented to the Instruction decoder.
