Take the Rough with the Smooth Part 2 (PIC Microcontroller)

The successive approximation network at the heart of the A/D converter is shown in a simplified form in Fig. 14.6. The step-by-step process is sequenced by a shift register (SRG, see Fig. 2.20) when the programmer sets the GO/DONE bit3 in the ADCON0 register (A/D CON-trol0).4 As the Control shift register is clocked, the single 1 moves down to activate each step in the sequence:

The capacitor network is switched to Hold and each capacitor, beginning with the largest value, is switched to Vref in turn. The outcome of the comparator then determines the state of the corresponding bit in the Successive Approximation Register (SAR). The process is detailed in Fig. 14.7. After eight set-try-reset actions, the outcome in the SAR is transferred to the Analog to Digital RESult (ADRES) register in File 0Ah. The GO/DONE flag is now cleared to indicate the End Of Conversion and the ADIF flag set. Finally, the analog input is again switched back into the capacitor network (Sample).

The total conversion time is approximately ten times the clocking rate tAD of the sequencer shift register. The minimum clocking period is 1.6 is (« 600 kHz) for all but the older 2 is PIC16C71/711 devices. There is no specified lower clocking frequency, but as charge slowly leaks away from the network capacitors, a tAD of more than nominally 20 is (50 kHz) should be avoided. From Fig. 14.8 we see that the ADC clock can be derived from one of four sources using the ADCS1:0 (A/D Clock Select) bits in the ADCONO SPR. The first three of these are fractions of the MCU clock rate and the fourth is a stand-alone CR oscillator with a nominal tAD of 4 is.

Fig. 14.6 Simplified view of the A/D converter.

One of the first tasks a programmer must do is to determine the clocking rate by setting the ADCS1:0 bits appropriately. Table 14.2 shows suggested settings for four typical PIC crystal frequencies. If A/D conversion time is critical then the PIC crystal may be chosen to give the fastest con-version time. For example, a 5 MHz crystal with ADCS1:0 = 01 gives a tAD of 1.6 is.

Table 14.2: ADC clocking frequency versus device crystal frequency.

ADC clock source tAD		PIC crystal frequency
	ADSC1:0	20 MHz
	00	—
	01	—
	10
	11

The internal ADC module CR clock is typically used where the main crystal is below 1 MHz. This separate clock source also allows a conversion to be completed when the PIC is in its Sleep mode, as the main processor oscillator is switched off in this situation. In this case the end of conversion interrupt can be used to awaken the MCU. This gives a relatively quiet environment during the conversion and for this reason is often used even where the processor crystal is above 1 MHz – see Program 14.4.

For lowest current consumption, especially during the Sleep mode, the ADC module should be switched off when not in use by clearing the ADON bit in ADCONO. ADON is cleared on Reset, so needs to be set when the module is to be activated.

The conversion process is illustrated in Fig. 14.7. As we have seen in Fig. 14.5, at the end of the sample period the top plates of the capacitor array are at -Vin and the bottom plates are disconnected but at zero potential. As an example let us assume that Vin is 0.4285Vref.

1. The process begins by switching in Vref into the lower plate of the largest capacitor as controlled by the SAR8 latch in Fig. 14.6. This causes an injection of charge AQ = CtotalVref, which is identical across both the 8-unit capacitor C] and the rest of the capacitors which also have a parallel value of 8 units in Fig. 14.7. Thus the voltage at node N rises by Vref/2 to -0.485 + 0.5 = +0.07125Vref. In general AVn = VrefCk/Ctotal. The comparator output is now logic 0 and the SAQ8 latch is consequently cleared, reversing the Vref/2 step.

2. SAQ4 switches Vref into the next highest capacitor giving a Vref/4 step at N (12). The resulting voltage of -0.485 + 0.25 = -0.178Vref giving a comparator output of logic 1 and SAR4 remains set with the node voltage staying at -0.1785Vref.

3. SAQ2 switches Vref into the second lowest capacitor giving a Vref/8 step at N (16). The resulting voltage of-0.1785+0.125 = -0.0535Vref giving a comparator output of logic 1 and SAR2 remains set with the node voltage staying at -0.0535Vref.

Fig. 14.7 The successive approximation process.

4. SAQ1 switches Vref into the lowest capacitor giving a Vref/16 step at N (jg). The resulting voltage of —0.0535 + 0.0625 = +0.009Vref giving a comparator output of logic 0 and SAR1 is cleared and the Vref/16 step is reversed.

The state of the SAR of 0110k or 0.375Vref represents the best 4-bit fit to Vin = 0.4285Vref. The residue 0.0535Vref is the quantizing error. Most MCUs use an 8-bit capacitor array. In principle the technique can readily be extended to higher resolutions, but in practice the difficulty in matching ever greater capacitors and internal logic noise means the majority of processors use 8-bit resolution. However, a few MCU devices2 do have 10 or 12-bit converters. External successive-approximation devices with 12 or more bits resolution, usually using a resistor ladder network, are readily available, but are relatively expensive.

Matching of the array capacitors, offsets and resistance of internal switches, leakage currents and analog comparator non-linearities all contribute to errors in the conversion process. It is beyond the scope of this text to analyze the various measures of error but the device data sheet lists absolute error, defined as the sum of all component error measures, as better than ±1 LSB. This guarantees that the transfer is monotonic; that is the binary code will never move in the reverse direction for any change AVin of input voltage. This error figure is for Vref = VDD; if Vref is lower than VDD then accuracy deteriorates, although values down to 3 V will give acceptable results in most cases. Accuracy can be improved, especially when the internal CR oscillator is used, if the conversion is done while the PIC is in its Sleep mode.

The standard PIC ADC module has eight input channels with any one selected for conversion according to the 3-bit Channel Select code CHS2:0 in the ADCON0 register, as shown in Fig. 14.8. 28-pin footprint PICs, such as the PIC16C73, can only access the bottom five channels. ThePIC16C71 line of 18-pin footprint3 and 12C67X devices have an earlier 4-channel module with CHS2 missing. The PIC16C774 uses ADCON0[1] as CHS3.

The input analog channels AN4:0 are shared with the Port A digital inputs RA4:0 and AN7:5 with PortE RE2:0 in 40-pin devices. AN3 is special in that it can be used as the reference voltage input if configured accord-inglyby PCFG0 = 1 (Port ConFiGuration) bit in the ADCON1 register. Like all port configuration registers it is normally set up only once at the beginning of the program and it is therefore located in the less convenient Bank1 Data memory. Any such low-noise external Vref should be in the range 3 V — VDD + 0.3 V – see Fig. 14.17. For best accuracy it should be as high as possible; a value of 5.12 V will give a 20 mV per bit resolution.

Fig. 14.8 The 8-bit 8-channel analog to digital conversion module.

A low cost option is to use the standard supply voltage VDD (PCFG0 = 0) as the reference voltage, thus freeing up AN3 for use as a normal analog input. To reduce noise, a 0.1-1 /F Tantalum electroytic capacitor should be used to decouple noise as close as possible to the VDD pin.

If less than eight analog channels are needed then some of the pins can be assigned as digital I/O port lines using the PCFG2:0 bits as listed in Table 14.3. For example, if PCFG2:0 = 100 then RA1:0 are both analog (AN1:0) and the rest are digital (RA4:2, RE2:0) as applicable, with VDD used as the reference.

On Reset all pins are set to accept analog signals (A). Pins that are reconfigured as digital I/O (D) should never be connected to an analog signal. Such voltages may bias the digital input buffer (see Fig. 11.2 ) into its linear range and the resulting large current could cause irreversible damage.

Table 14.3: Configuring the ADC port pins in the PIC16C73/74 devices.

PCFG2:0	AN7	AN6	AN5	AN4	AN3	AN2	AN1	AN0
	RE2	RE1	RE0	RA5	RA3	RA2	RA1	RA0
	A	A	A	A	A	A	A	A
	A	A	A	A		A	A	A
	D	D	D	A		A	A	A
	D	D	D	A		A	A	A
	D	D	D	D		D	A	A
	D	D	D	D		D	A	A
	D	D	D	D	D	D	D	D
	D	D	D	D	D	D	D	D

Other PIC devices with an ADC module may have different settings and numbers of PCFG bits. For example the 8-pin footprint PIC12C67X devices with a 4-channel ADC module can configure individual pins as analog or digital to best use scarce resources. The PIC16C71X line has only the two PCFG bits whilst the PIC16C774 has four.

Fig. 14.9 Configuring the analog inputs for Port A and Port E.

We can see from Fig. 14.9 that an I/O pin configured as an analog input from ADCON1 simply disables the digital input buffer (compare with Fig. 11.2 ). No other circuitry is affected. From this we can make the following deductions.

• A port pin configured as analog will read as logic 0 due to the disabled digital input buffer.

• The TRIS buffer is not affected and thus the appropriate TRIS bits should be 1 ; that is the direction of the port pins configured as analog should be set to input to prevent contention between the nalog Vin and the digital state of the Data flip flop.

• The ADC can read an analog voltage at the pin even if that pin has not been configured as analog. However, the still active digital input buffer may consume an excessive current outside of the device’s specification.

Using Fig. 14.8 as the programmer’s model we can now deduce the hardware-software interaction in order to action a conversion. Assuming first that interrupts are not being used, the following steps can be identified:

1. Configure ADC module.

• Set up port pins as analog/voltage reference (ADCON1).

• Select ADC conversion clock source (ADCON0).

• Select ADC input channel (ADCON0).

• Turn on ADC module (ADCON0).

2. Wait for the required acquisition time, typically 12 is.

3. Start conversion by setting the GO/DONE bit.

4. Wait for ADC conversion to complete by polling the GO/DONE bit for low.

5. Read the ADRES register.

6. For next conversion go to step 1 or step 2 as required.