One Bit at a Time Part 6 (PIC Microcontroller)

As an example, if we wish to transmit the three characters PIC then the following code fragment would implement our task. For convenience the assembler allows the programmer to represent ASCII codes in delimited single quotes to represent their ASCII equivalent, as described.

Handling serial communications this way is only really satisfactory for very simple situations. For example, if the RX pin is not continually monitored a transmission can be missed or synchronization lost. Also it is difficult to implement a full-duplex link. In addition the procedure is software intensive with most of the processing power being wasted in delay loops. The situation can be improved somewhat by using an internal timer to generate the baud delay and by using interrupt-driven techniques. However, the majority of 28+pin PICs have an integral communications port to automatically deal with asynchronous transmission.

One of the first applications of the then new LSI fabrication techniques in the late 1960s, was the implementation of a dedicated hardware asynchronous serial port known as the Universal Asynchronous Receiver Transmitter. The UART12 was already in production by the time microprocessors were developed. Most PCs, even in the 1970s, had a serial port implemented by a UART, as do current systems. As well as dealing with shifting, error checking and interrupt handling, most UARTs also have an integral baud-rate generator which can be set up in software to give the correct bit frequency.

Figure 12.19 shows a simplified model of the basic PIC USART – Universal Synchronous-Asynchronous Receiver Transmitter as the port has a synchronous mode (SYNC = 1) which will not be discussed here. The core of the USART is the Transmit and Receive registers and their 12Sometimes known as the Asynchronous Communication Interface Adapter or ACIA.

Fig. 12.19 The PIC USART configured for asynchronous communication.

Transmission

The transmitter logic is enabled when the TranSmit ENable (TXEN) bit in the TranSmit STAtus register (TXSTA[5]) at File 98h is set. To send a character the datum must be moved to the TranSmit data REGister (TXREG) at File 19h, whence it will be transferred to the Transmit shift register and shifted out of pin TX, which is shared with RC6. If a 9bit format is required the TX9 bit in TXSTA[6] must be set to 1 and the ninth bit placed in bit 0 of the same register before moving the lower eight bits into TXREG. If the Transmit shift register is not empty; that is it is in the process of shifting out a previous datum, then the new datum will remain in the TXREG buffer register awaiting the completion of transmission before being transferred.

Bit 1 of the TranSmit STAtus register reflects the state of the Transmit shift register whilst the TranSmit Interrupt Flag (TXIF) in bit 4 of the Peripheral Interrupt Register 1 (PIR1) is automatically set when the TXREG buffer is empty and ready for reloading. If an interrupt on TX buffer is empty is required, the corresponding TXIE mask bit in the Peripheral

Enable Register 1 (PIE1[4]) must be set – see Fig. 14.10. TXIF is automatically cleared whenever a datum is written into the TXREG.

Reception

Once a Start bit is detected at pin RX then the succeeding eight or nine bits are shifted into the 2-deep ReCeive data REGister (RCREG) at File 1Ah pipeline irrespective of what is going on at the transmitter section. If a 9-bit receive protocol has been selected with RX9 set to 1 in RCSTA[6] then the ninth bit can be read in the RX9D bit of the same status register.

When a datum has been received, it is automatically stored in the top RCREG buffer whence it moves to the lower buffer, provided that no datum is still waiting to be read. ReCeiver Interrupt Flag (RCIF) is automatically set whenever a datum is waiting for collection and this can be used to generate an interrupt if the RCIE mask bit is set; as well as the GIE and PEIE global masks. RCIF is cleared whenever a datum is read. If a datum is waiting in the top buffer, then RCIF is immediately set again showing that there is another datum ready for collection.

If a third character has been received and the 2-deep receive pipeline is full then the Overflow ERRor (OERR) bit at RCSTA[1] will be set and this newly received datum will be lost. The RCREG can still be read twice to retrieve the two buffered bytes. However, to clear OERR the receive logic must be reset by clearing the Continuous Receive ENable (CREN) bit in RCSTA[4] and then setting it again.

The Framing ERRor (FERR) bit in RCSTA[2] will be updated by reading the RCREG on the next received datum. Both FERR and any ninth received bit are double buffered in the same way as the received data and so should be read/checked first before the main datum is read as this will empty the pipeline and therefore change these auxiliary bits.

Serial Port Baud-Rate Generator, SPBRG

This is basically a programmable 8-bit counter followed by a switchable frequency -M flip flop chain which can be set up to give the appropriate sampling and shifting rates for the desired baud rate, based on the PIC’s crystal frequency XTAL giving:

where Xis an 8-bit datum written into SPBRG at File99h who’s value isFor example, if we require a baud rate of 4800 on a 20 MHz device, then a value X = 64 will give a baud rate of 4808, an error of +0.161%. At 20MHz the maximum baud rate is 312,500 whilst the lowest rate is 1221. A baud rate of 1.25Mbaud is obtainable at 20MHz in the high-speed mode with SPBRG = 1, but Microchip do not advise this mode for older devices, such as the PIC16C74/74A,13 as receive errors can occur.

Actually, the SPBRG produces higher frequencies than the base baud rate, to enable the USART to take three samples around bit midpoints and adopt a majority decision. In the low-speed mode a sampling rate of X16 is used, as is the case for newer devices in the high-speed mode. Older devices use X 4 for the high-speed mode.

To illustrate how to use the USART we will repeat our GETCHAR and PUTCHAR subroutines using hardware. Firstly, in the main program we have to set up the Serial Port Baud Rate Generator and both Transmit and Receive Status/Control registers. Assuming, as in Program 12.10, the programmer has defined the constants XTAL and BAUD then we can let the assembler evaluate the arithmetic to give us the value of X to put in the SPBRG. With this in mind, the initialization code would look something like:

With the USART enabled the subroutines are coded in Program 12.12. PUTCHAR is simply a matter of polling TXIF waiting for it to go to 1 and then copying the datum to the TranSmitter REGister.

The input GETCHAR is a little more complex if some error checking is to be incorporated. The subroutine polls the state of RCIF which goes to 1 whenever there is data to be read. Also returned is the variable ERR which is 00h if there is no problem, -1 if a Framing error occurred, -2 if a Overflow situation is sensed and – 3 if both errors occurred. In these latter situations OERR is zeroed by resetting the receiver logic. After the error conditions have been checked the data is read from the ReCeive REGister. This is done after checking to avoid altering the appropriate error flags.

Program 12.12 The USART-based I/O subroutines.

Some systems may not wish the processor to hang up waiting for a character which is a long time in coming. In such cases an alternative input subroutine, perhaps called getch, could return an ERR of -1 if the return was empty handed. Another approach would be to generate an interrupt each time an incoming character is sensed rather than using a polling technique.

In the case of the CCS C compiler the #use rs232 directive tells the compiler which pins are to be used for RX and TX. The normal C I/O functions, such as printf(), use these pins as their link to the standard channel. If these pins are specified as PIN_C6 and PIN_C7 then where the part has a built-in USART this will be used instead of a software technique.

There is more to setting up a communication link than establishing a suitable protocol. PIC devices have normal logic voltage and current levels which are not intended for connections greater than 30 cm (1′). Although with care14 distances considerably in excess of this can be employed, in situations with relatively fast bit rates different signalling techniques have to be used.

In the era of electromechanical TTYs the de facto 20 mA loop standard was in common use. This uses zero and 20 mA current to signal logic 0 and logic 1 respectively. Use of current means that line attenuation is not a problem (as current out must equal current in) and this level of current was sufficient to directly activate the receiver solenoid relay.

Current sources are realized by using high voltages in series with a large resistance. The latter gives long time constants, which, while adequate in the area of 110 baud rates, did not transfer well to the introduction of electronic terminals, UARTs and modems. RS-23215 was introduced in 1969 as the standard interface for connecting an item of Data Terminal Equipment (DTE), such as a terminal, to approved Data Circuit terminating Equipment (DCE), typically a modem. Thus, not only did it define signalling levels, as shown in Fig. 12.20(a), but also various control and handshake lines, some of which are shown in Figs. 12.20(d) and 12.21. For example the modem would signal back to the DTE that a telephone link had been opened with the remote DTE by activating the Clear To Send (CTS) handshake signal. Two data lines plus a ground line are needed for a full duplex transmission circuit.

The RS-232 standard has a range of 15 m (50′) at a maximum rate of 20 kbaud, which it achieves by mapping logic 0 (often called a space) to typically +12 V and logic 1 (often called a mark) to typically -12 V. The receiver can distinguish levels down to ± 5 V. The RS-423 standard (1978) in Fig. 12.20(b) is similar but can manage 1.2 km (6000′) at up to 80 kbaud and 10Mbaud at 12 m (40′) with up to ten receivers.

Both RS-232 and RS-423 are unbalanced (or single-ended) standards, where the receiver measures the potential between signal line and ground reference. Even though the transmitter and receiver grounds are usually connected through the transmission line return, the impedance over a long distance may support a significant difference in the two ground potentials, which will degrade noise immunity. Furthermore, any noise induced from outside will affect signal lines differently from the ground return due to their dissimilar electrical characteristics – hence the name unbalanced.

 

Fig. 12.20 Some signalling configurations.

The RS-422 (1978) and RS-485 (1983) standards are described as balanced. Here each signal link comprises two conductors, normally twisted around each other, known as twisted pair. The logic level is represented as the difference of potential across the conductors, not the difference from ground. Calling the conductors A and B, then logic 0 is represented as A<B and logic 1 by A>B. A difference of more than ±200 mV at the receiver is sufficient to establish the logic level and the transmitter will typically generate a A V =± 5 V. As the A and B conductors have the same characteristics and are tightly wound together they represent similar targets for induced noise. As the same noise voltage appears in both conductors and the receiver only distinguishes differences, rejecting common-mode voltages up to ±7 V, then the noise immunity of these balanced links is clearly superior to unbalanced schemes. Commercial twistedpair cables, used in Local Area Networks (LANs), often carry three or four pairs of conductors, each link having a different twist pitch to reduce induction between links.

The main difference between the RS-422 and RS-485 standards is the provision in the latter case for multiple transmitters as well as receivers to implement multi-drop LANs. As only one transmitter can be active at any one time, an RS-485 transmitter buffer must have an enable input, to select the master device. The single RS-422 transmitter has no need to be disabled.