INTRODUCTION
A bottom-up approach, in which functional systems are assembled from chemically synthesized, well-defined nanoscale building blocks, has the potential to go far beyond of the limits of top-down technology by defining key nanometer scale metrics through synthesis and subsequent assembly—not by lithography. One-dimensional (1D) nanostructures represent the smallest dimension structure that can efficiently transport electrical carriers and can play an important role as both interconnect and functional device elements in integrated nanosystems. Here, we review recent advances in bottom-up assembly of nanoscale electronics and optoelectronics using semiconductor nanowire (NW) as building blocks. First, we review electrical transport studies on individual NWs, and moreover, examine nanoscale electronic and optoelectronic devices assembled using individual NWs as building blocks. Next, we present approaches for the hierarchical assembly of NWs into well-defined arrays with controlled orientation and spatial location. Third, we address critical issues for integration and demonstrate the assembly of integrated nanoscale devices with logic and computation circuits. Lastly, we describe a unique application enabled by nanoscale NW devices: highly sensitive and selective chemical and biological sensing. We conclude with a brief summary and perspective on future opportunities.
BACKGROUND
Top-Down Technology: The Limitations
The rapid miniaturization of electronics to the submicron scale has led to remarkable advances in computing power while at the same time reducing costs. These advances have been made possible by many scientific and technological innovations associated with "top-down” manufacturing, in which small features are patterned in bulk semiconductor materials by lithography, deposition, and other processing to form functional devices. This now remarkable trend in miniaturization was first pointed out by Gordon Moore, and is now universally referred to as Moore’s Law, which dictates that the number of transistors per chip doubles every 18-24 months (Fig. 1).[1,2] The magnitude of what has been accomplished can be recognized by the fact that it is now possible to fabricate a 100 million transistors on a chip of the same size as a single transistor when it was first invented a half century ago. However, as the microelectronic industry advances towards ever smaller devices, it is believed that physical and economic limits of current top-down silicon technology will be soon reached. First, photolithography-based top-down strategies will soon reach a fundamental resolution limit of ca. 70 nm that will limit further reduction in feature sizes using relatively conventional optical sources, although solutions such as extreme ultraviolet lithography are being explored to overcome this limit. Second, the exponentially increasing cost to construct each new generation of fabrication line may limit further miniaturization on the basis of economics alone. These and other limitations of current top-down technology have motivated efforts worldwide to search for new strategies to meet the expected demand for increased computational power as well as for integrating low-cost and flexible computing in unconventional environments in the future.[3-5]
Bottom-Up Technology: Requirements and Promises
To go beyond the fundamental and economic limitations of top-down technologies will require new methods.
Fig. 1 Illustration of device scaling in conventional electronics—Moore’s law.
A bottom-up approach, in which functional electronic structures are assembled from chemically synthesized, well-defined nanoscale building blocks, much like the way nature uses proteins and other macromolecules to construct complex biological systems, represents a flexible alternative to conventional top-down methods,[4'6'7] and moreover, the bottom-up approach has the potential to go far beyond the limits of top-down technology by defining key nanometer scale metrics through synthesis and subsequent assembly— not by lithography.
To enable this bottom-up pathway requires that three key problems, which are at the heart of devices and integration in the broadest terms, be addressed (Fig. 2). First, the bottom-up approach requires nanoscale building blocks with precisely controlled and tunable chemical composition, structure, morphology, and size, since these characteristics determine their corresponding electronic and optical properties. To meet this goal necessitates developing methods that enable rational design and predictable synthesis of the building blocks. Second, it is essential to develop and explore the limits of functional devices based on these building blocks. Nanodevices may behave in ways similar to current electronic and optoelectronic devices, although it is also expected that new and potentially revolutionary device concepts will emerge from these building blocks, for example, due to quantum properties. Third and central to the bottom-up concept is the development of device architectures that enable high-density integration with desired function, and the development of hierarchical assembly methods that can organize building blocks into these architectures.
Fig. 2 Schematic outlining key challenges (open ellipses) and specific research areas (shaded ellipses) required to enable the bottom-up approach to nanoelectronic systems.
Addressing and overcoming the hurdles in these three major areas of the bottom-up approach could revolutionize fabrication and manufacturing, make a quantum jump in miniaturization, and lead to reduced power consumption and increased speed in next generation electronics and photonics. Moreover, it is very likely that the bottom-up approach could enable entirely new device concepts and new systems. For example, it is possible to combine seamlessly chemically distinct nanoscale building blocks, which could not be integrated together in top-down processing, into the same device architecture and thereby obtain unique function and/or combinations of function in an integrated system. Small and highly perfect building blocks may also lead to quantum electronic or quantum optical devices that enable quantum computing in an architecture that has many common features with digital systems.
Nanoscale Building Blocks
Individual molecules[8-12] and quantum dots,[13-15] which can be classified as zero-dimensional (0D) structures, have been proposed as building blocks for bottom-up assembly of nanoscale electronics. These 0D structures have been intensively pursued over the past decade since they represent the smallest building blocks with corresponding high potential for massive integration. However, the use of individual molecules or quantum dots in nanoelectronics has been limited by challenges in establishing reliable electrical contacts needed to study their fundamental properties and interconnect them. It has thus been difficult to elucidate and understand the intrinsic properties of individual devices, and moreover, to develop and demonstrate realistic schemes for scalable interconnection and integration of 0D devices into functional architectures.
One-dimensional nanostructures have also been the focus of extensive studies worldwide due to their unique physical properties and potential to revolutionize broad areas of nanotechnology. First, 1D nano-structures represent the smallest dimension structure that can efficiently transport electrical carriers, and thus are ideally suited to the critical and ubiquitous task of moving and routing charges (information) in nanoscale electronics and optoelectronics. Second, 1D nanostructures can also exhibit device function, and thus can be exploited as both the wiring and device elements in architectures for functional nanosys-tems.[4,16] In this regard, two material classes, carbon nanotubes (NTs)[16-27] and semiconductor NWs,[28-35] have shown particular promise.
Single-walled carbon NTs can exhibit either metallic or semiconducting behavior depending on diameter and helicity.[17] The unique electronic properties of NTs open up the possibility of creating a number of different devices that could have potential in nanoelec-tronics.[16,18-20] For example, single-walled NTs have been used to fabricate room-temperature field effect transistors (FETs),[21,22] diodes[23,24] and recently, logic circuits.[25,26] However, the inability to control whether NT building blocks are semiconducting or metallic makes specific device fabrication largely a random event. Hence, moving beyond proof-of-concept single device elements to the integrated arrays required for nanoelectronics poses a serious issue for NT-based approaches. A creative solution to the problem of coexisting metallic and semiconducting NTs involves selective destruction of metallic tubes,[27] although such an approach requires extensive top-down lithography and subsequent processing to implement and may not be practical for highly integrated nanoelectronics systems.
Semiconductor NWs[4,28,29] represent another important type of nanometer scale wire structure. In contrast to NTs, however, semiconductor NWs can be rationally and predictably synthesized in single crystal form with all key parameters controlled, including chemical composition, diameter and length, and doping/electronic properties.[30-32] Semiconductor NWs thus represent one of best-defined and controlled class of nanoscale building blocks, which correspondingly have enabled a wide range of devices and integration strategies to be pursued. For example, semiconductor NWs have been assembled into nanometer scale FETs,[32,33] p-n diodes,[33,34] light emitting diodes (LEDs),[33] bipolar junction transistors,[34] complementary inverters,[34] complex logic gates, and even computational circuits that have been used to carry out basic digital calculations.[35] In contrast to NTs, NW devices can be assembled in a rational and predictable manner because the size, interfacial properties, and electronic properties of the NWs can be precisely controlled during synthesis, and moreover, reliable methods exist for their parallel assembly.[36] In addition, it is possible to combine distinct NW building blocks in ways not possible in conventional electronics and to leverage the knowledge base that exists for the chemical modification of inorganic surfaces[37,38] to produce semiconductor NW devices that achieve new function and correspondingly could lead to unexpected device and system concepts.
Overview
In this topic, we describe a broad range of studies addressing nanoelectronics and nanophotonics assembled from semiconducting NW building blocks. First, we review electrical transport studies of individual NWs, and moreover, examine nanoscale electronic and optoelectronic devices assembled using individual NWs as building blocks. Next, we present approaches for the hierarchical assembly of NWs into well-defined arrays with controlled orientation and spatial location. Third, we address critical issues for integration and demonstrate the assembly of integrated nanoscale devices with logic and computation circuits. Lastly, we describe an application enabled today by nanoscale NW devices: highly sensitive and selective chemical and biological sensing. We conclude with a brief summary and perspective on future opportunities.
NANOWIRE ELECTRONIC DEVICE ELEMENTS
In a previous topic, we have reviewed the rational synthesis of semiconductor NWs. The availability of a wide range of NW materials with controlled chemical composition, physical size, and electronic properties opens up many exciting opportunities ranging from fundamental studies of the role of dimensionality on physical properties to a range of potential applications in areas such as nanoscale electronics and optoelectronics. In the section, we focus on fabrication and electrical transport properties of basic nanoscale device elements fashioned from these NW building blocks, including 1) single NW-FETs, 2) crossed NW p-n diodes, intra-NW p-n diode, 3) bipolar transistors, 4) crossed NW-FETs, and 5) NW quantum interference devices.
Nanowire Field Effect Transistors
Device structure and underlying principles
The basic FET structure fabricated from single semiconducting NWs is illustrated in Fig. 3. The FET is supported on an oxidized silicon substrate with the underlying conducting silicon used as a global back gate electrode to vary the electrostatic potential of the NW. In a typical NW-FET device (Fig. 3, inset), two metal contacts, which correspond to source and drain electrodes, are defined by electron beam lithography followed by evaporation of suitable metal contacts. Current (I) vs. source-drain voltage (Vsd) and I vs. gate voltage (Vg) is then recorded for a NW-FET to characterize its electrical properties.
Fig. 3 Schematic of a NW-FET. Inset: SEM image of a NW-FET; two metal electrodes, which correspond to source and drain, are visible at the left and right sides of the image.
Fig. 4 (A,B) Band diagrams illustrating the underlying principle for p- and n-channel NW-FETs. When a positive voltage is applied, the bands are lowered, which depletes the holes in p-NWs and suppresses conductivity, but leads to an accumulation of electrons in n-NWs and enhances the conductivity. Conversely, a negative gate voltage will raise the bands and increase the conductivity of p-type NWs and decrease the conductivity of the n-type NWs.
Variation of Vg during characterization of the NW-FET enables important qualitative and quantitative properties to be elucidated. For example, changes in Vg produce variations in the electrostatic potential of the NW, and hence change the carrier concentration and conductance of the NW. As shown in Fig. 4, p-and n-type semiconductor NWs, which are contacted at both ends to metal electrodes, respond in opposite ways to the applied gate. When a positive Vg is applied, the bands are lowered, which depletes the holes and suppresses conductivity in p-NWs, but leads to an accumulation of electrons and an enhancement in conductivity in n-NWs. Conversely, a negative Vg will increase the conductivity of p-type NWs and decrease the conductivity of the n-type NWs.
p-Channel nanowire transistors
Typical I vs. Vsd data obtained from a single boron-doped Si NW-FET at different Vgs are shown in Fig. 5. The two-terminal I-Vsd curves are linear, which indicates that the metal electrodes make ohmic contacts to the NW, and moreover, the gate response demonstrates that the NW is p-type; that is, the conductance of the p-Si NW decreases (increases) with increasingly positive (negative) Vg. The transfer characteristics, I-Vg, of p-Si NW devices (Fig. 5, inset) exhibit behavior typical of p-channel metal-oxide-semiconductor FETs (MOSFETs).[39] Significantly, the conductance modulation of the p-Si NW-FET exceeds 103, where the Vg required for switching (-10 to 10 V) could be reduced significantly by reducing the thick (600 nm) oxide dielectric layer in these back-gated devices (see below).
Gate-dependent measurements have also been used to estimate the hole concentration in p-channel NW-FETs. The total NW charge can be expressed as Q = C • Vth, where C is the NW capacitance and Vth the threshold gate voltage required to deplete completely the NW. The capacitance is given by C ffi 2pee0L/ln(2h/r), where e is the effective gate oxide dielectric constant, h is the thickness of the SiO2 layer on the substrate, L is the NW length, and r is the NW radius. The hole density, nh = Q/(e • pr2L), is estimated to be — 1018/cm3 for the device shown in Fig. 5. In addition, it is possible to estimate the carrier mobility of the NW-FETs from the transconductance dI/dVg = m(C/L2) Vsd, where m is the carrier mobility. Plots of dI/dVg vs. Vsd are linear for Si NWs, as expected for this model, yield hole mobilities in the range of 50-800 cm2/V sec. Significantly, the p-Si NW-FET mobilities are comparable to or larger than the best p-Si planar devices, 100-300 cm2/V sec, at comparable hole densities (p – 1017-1018/cm3).[40]
Fig. 5 Current vs. voltage for a p-type Si NW-FET. The numbers inside the plot indicate the corresponding gate voltages (Vg). The inset shows current vs. Vg for Vsd of 1 V.
n-Channel nanowire transistors
It is also possible to assemble n-channel NW-FETs in a similar way from n-type NWs. For example, gate-dependent I-Vsd data recorded from an InP NW-FET exhibits increased conductance for positive Vg and decreased conductance for negative Vg (Fig. 6), as expected for an n-channel device. The n-InP NW-FET transfer characteristics (I—Vg) show that the current increases rapidly from below 1 nA at Vg = -2 V to above 400 nA at Vg = +2V (Fig. 6, inset), and tends to saturate at higher voltages, which can be attributed to contact resistance and other factors. Nevertheless, the conductance changes up three orders of magnitude for only a few volts’ change in the gate voltage in these unoptimized devices.
The electron concentration and mobility in the n-channel NW-FETs have been estimated as described above for p-channel devices. For the n-InP NW-FET shown in Fig. 6, the electron mobility is 2200 cm2/V sec sec for an electron concentration of -1018/cm3. Studies of a number of different devices yields mobility values from 400 to 3000 cm2/V sec, which is comparable to or larger than bulk InP, 1000-2000 cm2/V sec, at similar carrier concentrations.[40] These mobilities are believed to represent a lower limit in our NW materials since the contact resistance and surface depletion have not been included. Significantly, surface passivation studies suggest that substantially higher carrier mobilities are possible in the NW-FETs. Taken together, these results suggest that the NW-FETs could be essential elements in high performance (e.g., high gain, high speed and low power) nanoelectronics and photonics.
Fig. 6 Current vs. voltage for an n-type InP NW-FET. The numbers inside the plot indicate the corresponding gate voltages (Vg). The inset shows current vs. Vg for Vsd of 0.1 V.
Crossed Nanowire p-n Diodes
The availability of well-defined n- and p-type NW building blocks opens up the possibility of creating complex functional devices by forming junctions between two or more wires. To explore this exciting opportunity, we have studied the transport behavior of n-n, p-p, and p-n junctions formed by crossing two n-type, two p-type, and one n-type and one p-type NW, respectively (Fig. 7A).[33] Significantly, the types of junctions studied in an experiment are reproducible since we can select the specific type of NW used at each of the two stages of device assembly.
Fig. 7 Crossed NW junctions. (A) SEM image of a typical crossed InP NW device with four metal electrodes contacted to each of the four arms. (B-D) I-V behavior of n-n, p-p, and p-n junctions, respectively. The I-V behavior of individual n- and p-NWs in the junctions is indicated by "n” and "p”, respectively. The I-V behavior across the junctions is designated by ”n-n”, "p-p,” and ”p-n.” The solid lines represent transport behavior across one pair of adjacent arms, and the dashed lines represent that of the other three pairs of adjacent arms.
First, I-V data recorded on the individual NWs in n-n and p-p crossed junctions show linear or nearly linear I-V behavior (Fig. 7B,C), indicating that the metal electrodes used in the experiments make ohmic or nearly ohmic contact to the NWs. This point is important since it shows that the NW-metal contacts will not make nonlinear contributions to the I-V measurements across the nanoscale junctions. In general, transport measurements recorded across the n-n and p-p junctions show linear or nearly linear behavior. These results indicate that interface oxide between individual NWs does not produce a significant tunneling barrier since a tunneling barrier would lead to highly nonlinear I-V behavior. In addition, the I-V curves recorded through each pairs of adjacent arms show similar current levels, which are smaller than that of the individual NWs themselves, demonstrating that the junction dominates the transport behavior. Taken as a whole, these data show that individual NWs can make good electrical contact with each other, despite the small contact area (10~12-10~10cm2) and simple method of junction fabrication.
Initial studies designed to probe the utility of this new approach for creating functional devices were focused on p-n junctions from crossed p- and n-type NWs. These junctions can be made reproducibly by sequential deposition of dilute solutions of n- and p-type NWs with intermediate drying. Typical I-V behavior of a crossed InP NW p-n junction is shown in Fig. 20D. The linear I-V of the individual n- and p-type NWs components indicates ohmic contact between the NWs and metal electrodes, while transport across the p-n junction shows clear current rectification; that is, little current flows in reverse bias, while there is a sharp current onset in forward bias. Significantly, this behavior is similar to conventional semiconductor p-n junctions. In a standard p-n junction, rectification arises from the potential barrier formed at the interface between p- and n-type materials.[39] In the case of our crossed NW p-n junctions, this picture is probably modified due to the presence of some interface oxide (Fig. 8), although a thin oxide will not change substantially the overall I-V response.
The assignment of the observed rectification to the p-n junction formed at the crossing point between p-and n-type InP NWs was further supported by several other pieces of evidence. First, the linear or nearly linear I-V behavior of individual p- and n-type NWs shows that ohmic contacts were been made between the NWs and metal electrodes, and thus exclude the possibility that rectification arises from metal-semiconductor Schottky diodes.[39] Second, the I-V behavior of the junction determined through each pair of adjacent electrodes (Fig. 7D) exhibit similar rectification and current level, which is also much smaller than the current through individual NWs, demonstrating that the junction dominates the I-V behavior. Third, four-terminal measurements in which current is passed through two adjacent electrodes while the junction voltage drop is measured across the two remaining electrodes exhibit similar I-V and rectification with only a slightly smaller voltage drop (0.1-0.2 V) compared to two-terminal measurements at the same current level. Fourth, measurements made on over 20 independent InP crossed p-n junctions showed similar rectification in the I-V data. Lastly, the formation of crossed NW p-n junctions is not by any means restricted to InP NWs, and is general to the wide range of materials. For example, p-n junctions have been assembled from p-Si/n-Si,[34] p-Si/n-GaN,[35] p-Si/ n-InP, p-Si/n-CdS, and p-Si/n-CdSe NWs,[41] and transport measurements have demonstrated that all of these crossed p-n junctions show consistent current rectification behavior.
Bipolar Junction Transistors
Since p-n junctions represent a basic element in many functional electronic devices, including amplifiers and switches, we have explored the possibility of assembling such devices at nanometer scale using the well-defined p- and n-type NW materials. As an example, integrated bipolar transistors,[34] which are active devices capable of current gain, have been assembled from three distinct types of Si NWs in the form of two crossed junctions (Fig. 9A). A conventional bipolar transistor requires three distinct material types. For example, in n+-p-n structure, a highly doped n+ layer is used as an emitter (E), a p-type layer for the base (B), and an n-type layer for the collector (C).[39] Significantly, this n+-p-n basic structure can be easily assembled with Si NWs since NWs with controlled doping type and doping concentration are available (Fig. 9C, inset).[32]
Fig. 8 Band diagrams of the crossed NW p-n junction. (A) Band bending occurs prior to for p-n contact due to surface Fermi level pinning; the bands bend further when the p- and n-type NWs come into contact to achieve equilibrium; (B) band bending in a clean p-n junction structure.
Fig. 9 Bipolar junction transistors. (A) Schematic illustrating the common base configuration of an n+-p-n bipolar transistor built from crossed Si NWs. (B) Collector current vs. collector-base voltage recorded on an n+-p-n transistor with emitter and collector Si NWs 15 mm apart. The numbers inside the plot indicate the corresponding emitter-base voltages. (C) The common base current gain vs. collector-base voltage. Inset: Typical SEM image of Si NW bipolar transistors.
To characterize the electrical behavior of assembled NW bipolar transistors, the individual Si NW building blocks and p-n+ and p-n junctions were first tested, and found to exhibit ohmic or nearly ohmic metal contacts and rectification, respectively. The bipolar transistor characteristics were then assessed from measurements of the collector current as a function of C-B voltage (Fig. 9B), while the n+ Si NW emitter was biased at different values. In general, the collector current is relatively constant (vs. C-B voltage) in the region from 0 to 6 V, which corresponds to the collector in reverse bias with only a very small leakage current, and this current value increases as the emitter forward bias/injected current is increased. The large collector current in reverse bias demonstrates these simple Si NW-based bipolar transistors exhibit behavior similar to that found in standard planar devices, and moreover, can exhibit very good current gain. The common base current gain, which is defined as the ratio of the collector current to emitter current (Fig. 9C), and the common emitter current gain, which is defined as the ratio of the collector current to base current, were found to be 0.94 and 16, respectively. The relatively large current gain observed in these simple devices suggests several important points. First, the efficiency of electron injection from emitter to base must be quite high, and can be attributed to the controlled NW doping that yields the desired n+-p E-B junction. Second, large current gains have been achieved in devices with large (e.g., 15 mm) base widths. This fact suggests that the mobility of injected electrons can be quite high in the Si NWs and is consistent with the direct mobility studies described above. These observations also indicate clear directions for improving the Si NW bipolar transistors. For example, it will be interesting to study the current gain as a function of base width, because it is easily possible to assemble structures with separations of the n+ and n-NWs of the order of 100 nm or less.
Crossed Nanowire Field Effect Transistors
A major motivation underlying research on nanoscale devices is to achieve integration at densities higher than possible with current technologies. The NW-FETs discussed above represent nanoscale analogs to conventional MOSFETs and have been very useful for testing basic device behavior (e.g., doping type and carrier mobility). However, the basic device structure of the NW-FETs and similar NT FETs[21,22] requires lithography to define metallic source-drain electrodes, and use either a global back gate (i.e., the doped silicon substrate) or lithography to define a more local gate. These design and fabrication features pose serious problems for integration. First, lithographically defined metal electrodes (i.e., source, drain, and gate) will limit integration to a level similar to that of conventional silicon technology. Moreover, the use of global back gate electrodes eliminates the possibility of independently addressing individual devices, and thus is incompatible with integration in most architectures.
Direct assembly of highly integrated functional electronic circuits based on NWs requires the development of new device concepts that are amenable to scalable integration. To this end, we recently developed a novel crossed NW-based FET.[35] A crossed NW-FET (cNW-FET) is assembled from two NWs where one or both have an oxide coating that serves as the gate dielectric (Fig. 10A,B). This approach is quite flexible since nano-FETs can be readily assembled with p- or n-type active channel NWs and the gate NW can also be p- or n-type independent of the channel. For example, using n-type GaN crossed NW as the gate for a p-type Si NW, a p-channel cNW-FET is formed with both a nanoscale channel and a nanoscale gate. Typical I-Vsd data recorded for different NW Vgs resemble the characteristics of a conventional depletion mode p-channel FET device (Fig. 10C). Notably, the conductance of the Si NW responds very sensitively to the voltage applied to n-NW gate, and can be changed by more than five orders of magnitude with a 1-2 V variation in the NW gate (Fig. 10D). In contrast, the conductance changed less than a factor of 10 for this same device when similar gate voltages were applied to the global back gate (Fig. 23D). The improved sensitivity can be attributed to the intrinsically thin gate dielectric between the two NWs. In addition, there is no leakage current from the n-NW gate when the cNW-FET is operated at low source-drain bias in the deletion mode since the crossed p-n junction is always reverse biased, and in this regard the device is similar to a junction FETs (JFETs).[39]
The cNW-FET represents an important new transistor concept for nanoelectronics. With this concept, three critical nanometer scale device metrics are naturally defined in assembled circuits without lithography: 1) a nanoscale channel width determined by the diameter of the active NW; 2) a nanoscale channel length defined by the crossed NW gate diameter; and 3) a nanoscale gate dielectric thickness determined by the NW surface oxide. Significantly, these distinct nanometer scale metrics are determined and can be controlled with near atomic precision during NW synthesis and subsequent assembly, and should enable higher gain, higher speed, and lower power dissipation devices than possible by conventional approaches. Moreover, the cNW-FET concept can be readily integrated in a parallel manner without lithography, thus enabling one to envision a straightforward way to nanometer scale integrated electronics of the future. Examples of more complex devices—logic gates— assembled from cNW-FET elements are discussed in section "Integrated Nanowire Devices”.
