IF Amplifier Measurement
The measurement of the IF amplifier has also been carried out on a PCB with an encapsulated IC. The connections of the IF amplifier have been made with the pins of the package specially made for the IF filter and the intermediate pads located next to the ADC.
Figure 4-28 shows the microphotograph of the IF amplifier. The figure shows the components of the IF amplifier: resistors, transistors, metal connections, and pads.
Figure 4-28 Microphotograph of the control logic measurement.
Figure 4-29 Test setup for measuring the gain of the first stage of the IF amplifier
The test setups required for measuring the performance of the IF amplifier are illustrated in Figures 4-29 and 4-30.
The gain and the power consumption of the amplifier can be measured with a sinusoidal input from a signal generator (Agilent E4421B) and a spectrum analyser (Agilent E4402B) with a high-frequency probe (Agilent 85024A), which presents an extremely low input capacitance of only 0.7pF shunted by 1MQ of resistance. Therefore, the standard 50Q of the spectrum analyser is avoided. Moreover, the probe allows direct measurement from the PCB. Consequently, no additional connectors are required on the PCB.
However, the insertion of the probe alters the load of the amplifier, thereby modifying its gain. To compare the experimental results with the values obtained from simulation, desginers should include the load added by the probe in the simulation environment. In this manner, the deviation from simulation results can be estimated for the amplifier’s real load during normal operation.
Figure 4-30 Test setup for measuring the gain of the second stage of the IF amplifier
TABLE 4-3 IF amplifier results
|
Specifications |
Post-layout |
Measurement |
Unit |
|
|
G |
 |
68 |
67 (47+20) |
dB |
|
Current |
3 |
2.4 |
2.5 |
mA |
The total gain of the IF amplifier is 67dB. This value is obtained in two stages: A gain of 47dB is introduced in the first IF amplifier stage and 20dB in the second IF amplifier stage. Both amplifiers have been measured separately. This is mainly due to the fact that the second stage of the IF amplifier lacks an output buffer and is therefore unable to amplify properly with the load modification introduced by the pads, bondwires, package leads, and the high-impedance probe.
Table 4-3 summarises the specifications and the post-layout and measurement results. It can be observed that the gain and the current specifications have been met.
ADC Measurement
The measurement of the ADC, either directly or separated from the rest of the RF front-end, is not possible through the use of any of the bonding configurations utilised for measurement.
The ADC is a simple 1bit converter that consists of just one D flip-flop. Its simulation was obtained from the 200-sample Montecarlo analysis and is expected to have a stable experimental performance.
Furthermore, the samples required for measuring the offset level of the ADC are unfeasible for the standard design process of an RF front-end (a MPW for the case of the design example of this topic). On the other hand, the correct performance of the ADC can be tested together with the entire front-end. A microphotograph of the ADC is shown in Figure 4-31.
Figure 4-31 Microphotograph of the control logic measurement.
Control Logic Measurement
As explained in the previous topic, different operation modes can be set by means of integrated logic. A microphotograph of integrated logic components is shown in Figure 4-32.
The performance of the control logic can be measured through the current consumption of the integrated circuit. Consequently, the current variation through the different operational states of the RF front-end can be measured.
The current consumption for the designed and fabricated IC is 23mA when the entire RF front-end is switched on. When in stand-by mode, the current consumption decreases to 0.5mA. When only the digital parts are on, the current consumption is 1.5mA in order to provide the clock signal. Finally, in the case of the test mode, the current consumption changes depending on the voltage applied to the Frequency Selection (FS) pin.
PLL Characterisation
The PLL plays a major role in the design of a dual RF front-end for a dual GPS and Galileo receiver with low-IF architecture, such as the one explained in this topic. The PLL is responsible for the frequency translation of the received signal. Among other undesired effects, it contributes, along with the phase noise, to the increase of the effective noise figure of the complete front-end and reduces its blocking performance. Therefore, before the characterisation of the complete RF front-end is attempted, it is mandatory to characterise the PLL separately.
To quantify the performance of the PLL integrated with the rest of the IC, intermediate pads located at the inputs and outputs of the PLL blocks are required. This enables the characterisation of both the PLL and its blocks.
Figure 4-32 Microphotograph of the control logic measurement.
The upper-left part of the microphotograph in Figure 4-4 shows the PLL, in which the intermediate pads can be easily identified. To measure output power, oscillation frequency, and current consumption, a test setup such as the one described in Figure 4-33 is required. In the case of the fabricated RF front-end, the results are described in the following paragraphs.
The current consumption of the PLL is around 8.7mA, from which the prescaler consumes approximately 2mA, the pierce oscillator less than 500|im, and the VCO 6.3mA.
The output power of the PLL is between -11dBm and -12.5dBm for the tuning range between 0.5V and 2.8V. The characteristics of the measurement test setup suggest that the actual performance of the PLL could be slightly better than the measured one. The measurement test setup uses a spectrum analyser, which presents a 50Q input impedance. The buffer of the VCO is usually designed to drive the mixer LO input and the divider of the PLL. Therefore, the load of the buffer presents higher impedance during normal operation. The buffer is an emitter follower stage. This configuration does not add any gain to the system but isolates the tank of the VCO from the output load. During this stage, a high-impedance tank is usually achieved, as is, consequently, large output power with reasonably low current consumption. An impedance of 50Q on the other side of the buffer slightly reduces the impedance of the resonance tank. This results in the reduction of the voltage swing of the signal by decreasing not only the output power but also by increasing the phase noise.
Regarding the characterisation of phase noise, using a set of batteries to provide the power supply is highly recommended. This minimises the possible noise introduced by the power supply system. The connection between the set of batteries and the PCB should be made with the shortest pair of twisted cables available, in the quietest electromagnetic environment possible.
Figure 4-33 Test setup for the characterisation of the current consumption, oscillation frequency, and output power of the PLL
Figure 4-34 Test setup for the characterisation of the phase noise of the PLL
Figure 4-34 illustrates the test setup utilised for the characterisation of the PLL phase noise.
The phase noise characteristic of the fabricated PLL is illustrated in Figure 4-35. The VCO, the divider, the PFD, the charge pump, and the loop filter are the main contributors to the total noise. The measured values show that at 100kHz from the fundamental tone, the phase noise is around -84dBc, which could be expected from the simulation results. Although the measured value is slightly higher than the specified one, such difference does not affect the performance of the receiver. This is explained in detail in the PLL design section (section 3.6) of the previous topic.
It is worth mentioning that although short, twisted cables are used with a set of batteries, spurious tones tend to be captured by the PLL feeding system. These spurious tones are translated to the side bands of the PLL output and distort the measured phase noise values. It is important to distinguish these tones because, as they are not introduced by the PLL, they should be discarded. These tones are usually caused by lightning systems, PCs, or other electronic equipment operating in the vicinity.
Figure 4-35 Phase noise response of the PLL
Table 4-4 summarises the specified values, the post-layout simulation results, and the measured characteristics. The value of the output power in the table corresponds to the value measured with the 50Q load of the spectrum analyser. The output buffer of the VCO has been designed to drive loads of the mixer and the divider of the PLL. Therefore, for a lower load, a lower value of the output power is obtained. However, the 50Q load of the measurement equipment and the additional bonding wires can be considered and included in the simulation environment. This results in the matching of the output power obtained from the simulation to the measured value. Therefore, it could be stated that the actual output voltage driving the mixer is within the specified range of 0dBm to 3dBm. On the other hand, if the output power were slightly lower than the value specified due to the characteristics of the mixer, the final performance of the receiver chain would hardly vary.
Though the measured frequency of the PLL range meets specifications, it is higher than that predicted by the simulations. This is due to the overestimation of the parasitic capacitances of the metal paths of the VCO. The safety margin introduced in the locking range of the PLL ensures the correct oscillation frequency of the PLL.
The second-order harmonic and the current consumption results are just slightly higher than the value specified and are therefore acceptable.
VCO Measurement The variation of the oscillation frequency with the tuning voltage of the VCO can be measured with the same bonding configuration of the PLL but without connecting the PLL filter to the tuning voltage pin of the VCO.
Figure 4-36 illustrates the test setup required for measuring the variation of the oscillation frequency with the tuning voltage.
TABLE 4-4 Specified characteristics of the PLL, values estimated from post-layout simulations and measured values
|
Parameter |
Specification |
Post-layout [2.8V/0.5V] |
Measurement [2.8V/0.5V] *with a 50W Load |
Unit |
|
Output power |
0-3 |
1.26/2.69 |
-11/-12.5 |
dBm |
|
Frequency |
1.544 & 1.571 |
1.513/1.729 |
1.509/1.750 |
GHz |
|
Phase noise |
-90 at 100kHz |
-97/-81 |
-84 |
dBc/Hz |
|
Second-order harmonic |
-23 |
-39/-37 |
-22.6 |
dBc |
|
Current Consumption |
<9 |
10 |
10 |
mA |
Figure 4-36 Test setup for measuring the oscillation frequency of the VCO for different tuning voltages
The output frequency is 1.750GHz for a control voltage of 0.5V and 1.509GHz for a control voltage of 2.8V. Both the working frequencies, 1554.960MHz and 1571.328MHz, lie within this range. The variation of the oscillation frequency with the tuning voltage is shown in Figure 4-37.
The gain constant (Kv) of the VCO is shown in Figure 4-38. The measured values presented in the figure demonstrate that both working frequencies are within the range of the VCO, proving that the VCO works properly for this application. The current consumption of the VCO is 6.3mA where the core itself requires 3mA.
Pulse Swallow Divider Measurement One of the blocks that is worth measuring is the pulse swallow divider. Most of the uncertainties related with the possible malfunction of a PLL disappear when characterising this block of the PLL. The measurement of this block provides a key insight into the performance of the local oscillator of the RF front-end. The test setup required for measuring the pulse swallow divider is illustrated in Figure 4-39.
Figure 4-37 VCO output frequency depending on control voltage
Figure 4-38 Variation of the gain constant of the VCO with the control voltage
In the fabricated RF front-end, the entire pulse swallow divider can be characterised as a whole. The sub-blocks that compose the pulse swallow divider (such as the prescaler, the program counter, and the swallow counter) cannot be separately measured in this design example.
The pulse swallow divider has to divide the signal frequency by 95 or 96, depending on the state of the control pin. Working frequencies have provided satisfactory results for the fabricated chip.
Special attention must be paid to filtering the noise coming from the power supply, which can cause the divider to malfunction, especially at higher frequencies. Higher robustness to power supply noise can be reached by minimising the parasitic capacitances of the circuit.
Figure 4-39 Test setup for measuring the performance of the pulse swallow divider
In addition, as explained in the circuit design, basic gates of the foundry library should be, in certain situations, modified to minimise their parasitic capacitance. This capacitance may create a delay in the signal that could make the divider slower than required. Moreover, parasitic capacitances of the prescaler’s D flip-flops also make switching time longer and thus not suitable for higher frequencies.
