In Depth Tutorials and Information

Circuit Design (GPS) Part 7

Phase Frequency Detector and Charge Pump

The output of an ideal PFD and charge pump is a current linearly proportional to the phase difference of the inputs, that is, the Xtal reference and the PLL feedback loop signal. Eq. 3-39 predicts the ideal behaviour of the PFD and charge pump illustrated in Figure 3-42.

where KPD is the PFD gain [A/rad] and Df is the input phase difference. Actually, the performance of the PFD is nonlineal and KPD depends on the amplitude or the duty cycle of the inputs.

Figure 3-42 (a) Block diagram of a PFD and charge pump; (b) characteristic of an ideal PFD and charge pump

The basic PFD consists of two D flip-flops and one AND gate, as shown in Figure 3-42. Depending on which input is high, the corresponding output will be also high; when both outputs are high, the flip-flops are reset. Thus, depending on the frequency difference, one output or the other will be high.

The charge pump consists of an NMOS transistor (M1), a PMOS transistor (M2), and two current sources (M3-M13) (see Figure 3-43).

Figure 3-43 Charge pump

Transistors Ml and M2 work as switches commuting the two equal current sources. If the up pulse (UU) is longer than the down pulse (DD), the former will be connected longer and current will flow to the loop filter capacitor. In a similar fashion, when the down pulse is longer than the up pulse, voltage will be decreased by means of the current sink, discharging the capacitor. In this manner, input phase difference is amplified by means of a change in the voltage control of the VCO. PFD gainis the charge pump current to the(1 cycle) ratio.

One of the drawbacks of this architecture is the dead zone. The dead zone is the phase difference between the PFD inputs that keep the charge pump (CP) from injecting or sinking current from the loop filter.

Figure 3-44 shows how, for phase differences belowthe current from the charge pump is zero. This effect increases the jitter at the output of the feedback loop, which produces an increase of the phase noise at the output of the PLL.

Figure 3-44 Dead zone effect of the PFD/CP

This effect happens for small phase differences in the inputs when the output pulses of the PFD are not wide enough to activate the charge pump. The most common method to eliminate the dead zone is the placement of an even number of inverters in the reset path (see Figure 3-42(a)), which introduces a delay big enough to activate the charge pump. Therefore, in the locked condition (Df = 0°), both outputs of the PFD (UU and DD) send pulses to the charge pump of equal width and amplitude. These pulses inject to and sink from the loop filter the same amount of current. As a consequence, the dead zone is eliminated without modifying the VCO control voltage. The minimum delay to be added has been estimated as the average of the up and down time pulses at UU and DD[Lee02].

It is also important to mention that to reduce the level of the spurious, the absolute value of the source and sink current sources should be as equal as possible[Razavi01].

Figure 3-45 shows the post-layout simulation of the output of the PFD. It shows the correct operation of the component with a current consumption of 27pA.

Figure 3-46 shows the output current and voltage of the charge pump. It can be seen how output voltage is increased and decreased depending on whether the current source switch is on or the current sink switch is on. The switches are controlled by the PFD output voltage.

Pierce Oscillator

The crystal oscillator provides the reference signal to the PFD and the clock signal to the ADC and the digital circuitry.

Figure 3-47 shows the architecture selected for the pierce oscillator; the components inside the square have been integrated in the chip.

Rbias is a feedback resistance providing DC bias for the inverter amplifier. Ci and C2 are the capacitors of the quartz crystal load and set the oscillating frequency together with the quartz crystal. R is the resistor employed to minimise the current flowing through the quartz.

The quartz crystal can be modelled electrically, as shown in Figure 3-48. Cp is the total capacitor between terminals, Ls is the vibrating mass of the crystal, and Cs is its elasticity. Rs represents the losses associated with the crystal. The output frequency depends on these values.

The standard characteristics of a crystal are shown in Figure 3-49.

The series resonance frequency is defined by Eq. 3-40, which is solely determined by the motional parameters of the crystal, Ls and Cs. The parallel resonance is higher than the series resonance and is defined by Eq. 3-41 where Eq. 3-42 is as shown.

Figure 3-45 PFD input and output signals for A^=+10ns. From the top to the bottom: Xtal, VCO/N, DD, and UU pulses.

Figure 3-46 Output voltage and current of the charge pump obtained from the post-layout simulation

Figure 3-47 Pierce oscillator

Figure 3-48 Quartz crystal equivalent circuit

Figure 3-49 Reactive characteristics of the quartz

The selected configuration makes the crystal work at the parallel resonance frequency.

where

To ensure oscillation, Barkhausen criteria has to be fulfilled, which defines that the gain must be higher than one and the phase must be equal to 0°. The inverter amplifier simultaneously provides a gain higher than one and a phase of 180°. Therefore, C1 and C2 capacitors provide another 180° to reach 0°[EXARDAN108]. To produce oscillation at the nominal frequency, the value of the capacitors has to be the same as the load capacitor (Eq. 3-43) given by the manufacturer. The remaining two inverters work solely as buffers.

The values of the components considered in the simulation are summarised in Table 3-14. For capacitors C1 and C2, parasitic resistance and inductance are also included. For these parameters, the oscillation is obtained with a current consumption of 0.7mA. The layout of the oscillator is shown in Figure 3-50.

TABLE 3-14 Values of the parameters of the pierce oscillator for the simulation