Once the design and fabrication of the receiver have been carried out, validation is required. This topic deals initially with the characterisation of the blocks and finally with the measurement of the whole front-end. The different test setups used are described with this objective in mind. Moreover, the required printed circuit board (PCB) and external components are also presented. Finally, the performance of the entire front-end is compared with that of a commercial one.
Introduction
When it comes to the characterisation of an integrated circuit (IC), it is mandatory to distinguish two stages: the test stage dedicated to the validation of the design, and the post-fabrication test stage that ensures the level of quality of the product.
This topic is dedicated to the first of the aforementioned stages, within which the following points will be described: on-wafer measurement techniques for passive elements, and testing techniques for both the different blocks of an encapsulated integrated circuit and the whole receiver chain.
Stages in the Validation of an Integrated Circuit Design
Multiple factors play a major role in the design of an integrated radio frequency (RF) front-end. Some of them are difficult to quantify and poorly described in industry literature. If these factors are not correctly considered, inefficient and expensive redesign loops may result, making the design of an IC unfeasible.
These factors include:
■ Accurate models of the passive elements included within the integrated circuit in the frequency range where they are expected to work Integrated inductors, varactors and RF pads with electrostatic discharge (ESD) protections are key elements to take into account.
■ The influence of the substrate on the performance of the different blocks of the IC. For example, the substrate noise coupling in the integrated spiral inductors and varactor of a voltage controlled oscillator (VCO) will degrade the phase noise performance of the local oscillator. In a similar way, the noise coupled through the substrate to the inductors of the low-noise amplifier (LNA) will increase the noise figure.
■ The influence that the different blocks encapsulated in the same package have on each other. For example, the current peaks required by the digital part of the local oscillator may couple through the power supply bondwires to the VCO and cause spurious tones in the phase noise response.
■ Influence of the bondwires. Underestimation or overestimation of the parasitic inductance associated with the bondwires may result in either a decrease or an increase in the gain of the single-ended stages.
To identify whether or not a design fails due to one of the previously mentioned factors, designers must establish a methodology to validate the design throughout several stages. The stages to be completed are:
■ Validation of the models of the integrated passive elements when not provided by the foundry.
■ Validation of the blocks that compose the RF front-end separately.
■ Validation of the blocks interacting with other blocks of the RF front-end.
■ Validation of the whole RF front-end.
Validation of Passive Element Models
Typically, foundries do not provide accurate models of passive elements for RF applications. Their models tend to leave out the following:
■ Inductors
■ Varactors
■ RF pads with ESD protections
The rest of the components of the integrated circuits (transistors, resistors, capacitors, etc.) are usually correctly modelled by the foundry and the data provided can be considered reliable.
Having a reliable model of these components should be considered essential prior to the design of the RF front-end blocks, such as the LNA and VCO.
An incorrect modelling of the integrated inductors may incur:
■ Divergences between the simulated and the measured linearity, gain, and noise figure in the LNA block.
■ Divergences among the phase noise, oscillation frequency, output power, and tuning range in the VCO block.
An incorrect modelling of the varactor may create divergences in the phase noise, oscillation frequency, output power, and tuning range in the VCO block.
An incorrect modelling of the RF pads with ESD protection may cause an important increase in the noise figure (NF) and an input impedance mismatch in the LNA.
The passive components should be measured on-wafer. The measurement process is widely detailed in [Aguilera03] and [Gutierrez07]. The necessary steps to be taken are briefly summarised as follows:
1. Design the measuring structure for the passive element (see Figure 4-1).
2. Design the de-embedding structure that eliminates the influence of the measuring structure from the passive element itself (see Figure 4-2).
Figure 4-1 Microphotograph of the integrated inductor (left) and varactor (right) inside the measurement structure
Figure 4-2 Microphotograph of the de-embedding structure for the integrated inductor and varactor
Figure 4-3 Photograph of the on-wafer test setup
3. Test setup calibration (see Figure 4-3).
4. Measure the passive element embedded in the measuring structure.
5. Measure the de-embedding structures.
6. Perform the data processing necessary to de-embed the passive element from the measuring structure.
7. Identify the electric model that describes the response of the passive element in the frequency range of interest once the influence of the measuring structure has been eliminated.
Individual Validation of Receiver Chain Blocks
Once the information about the passive elements has been obtained, the design and subsequent fabrication of the entire IC is possible.
The microphotograph of Figure 4-4 presents the complete RF front-end, the design of which is explained in the previous topic. The main components of this design example can be distinguished: the LNA, mixer,phased-lock loop (PLL), Intermediate Frequency Amplifier (IFA), and analogue-to-digital converter (ADC).
Figure 4-4 Microphotograph of the RF front-end for dual GPS and Galileo
It is worth mentioning that internal pads for the individual validation of the blocks have been specially included.
The IC is encapsulated in a TQFP48 package, mounted on a PCB that contains all the required external components for characterisation, as shown in Figure 4-5. These components include the decoupling capacitors, SAW filters, Xtal resonator, matching network, and connectors.
Figure 4-5 Packaged IC mounted on the PCB
Three different PCBs have been designed to characterise the different blocks separately. Thus, three different bonding diagrams for connecting the die to the package have been designed using the intermediate pads. Figure 4-6 illustrates the bonding diagrams.
The diagrams described in Figure 4-6 allow for the separate measurement of the different parts of the RF front-end.
As the bonding diagram in Figure 4-6(a) includes output digital pads and a disconnected PLL, the package pins of these sides can be connected to the intermediate pads located at the mixer LO input and the IF2 output. In this manner, RF and IF amplifiers and mixers can be measured separately from the rest of the front-end. Moreover, the LNA could also be measured with this configuration. However, the configuration shown in Figure 4-6(b) has been used for this approach.
Figure 4-6 Bonding diagrams for the individual characterisation of the receiver chain blocks: (a) test mode chip bonding diagram for measuring the RF amplifier+mixer and the IF amplifier; (b) test mode chip bonding diagram for measuring the LNA and the PLL; (c) test mode chip bonding diagram for measuring the front-end with an external Local Oscillator (LO).
The bonding diagram in Figure 4-6(b) shows the IF amplifier, the RF amplifier, the mixer, and the disconnected digital outputs. Therefore, the intermediate pads of the LNA and the PLL can be connected to the pins of the package. With the intermediate pads of the LNA, the output of the gain selection circuitry can be measured and the current of the LNA can be changed directly. The intermediate pads of the PLL are located at the output of the VCO and between the divider and the phase frequency detector so that the different parts of the PLL can be characterised separately.
Finally, in the bonding diagram shown in Figure 4-6(c), the PLL is not connected, allowing the measurement of the receiver chain with an external LO from the pin connected to the intermediate pads of the VCO output. Moreover, with the test mode of the control logic of the chip, the current of the front-end’s components can be modified, adding greater flexibility to the design characterisation.
