Layout Considerations and Simulation Results
Figure 3-22 shows the layout of the IF amplifier. Common centroid techniques and dummy structures have been employed to minimise any imbalance in the differential path.
TABLE 3-6 Size of the transistors and load resistor values for the first stage of the IF amplifier
|
Transistor |
 |
 |
 |
Resistor |
 |
 |
 |
 |
 |
 |
 |
TABLE 3-7 Values of IF filter components
|
L1 |
2.7pH |
L2 |
4.7pH |
|
C1 |
43pF |
C2 |
24pF |
Figure 3-22 IF amplifier microphotograph
Several ground contacts have also been placed between the different stages of the IF amplifier to minimise any coupling through the substrate that could cause the amplifier to oscillate. That is important as stages are placed close to each other and the gain is high (85dB). Finally, two internal pads have been placed at the output of the second IF limiting amplifier for test purposes. The size of the IF amplifier is approximately 630×270|im2.
Figure 3-23 shows the IF amplifier gain. It can be observed that it meets the gain specification set in the previous topic. Moreover, the band-pass shape centred in ~20.4MHz can be also observed. The -3dB passband bandwidth is 5.2MHz. Table 3-8 shows mean post-layout results and the specification values of the IF amplifier and filters. The amplifier gain has been oversized to enable the detection of the navigation signal in difficult environments such as a street surrounded by very high buildings. The passband bandwidth is smaller than the specified 6MHz. This fact will cause the C/N0 to degrade due to precorrelation filtering of only 0.2dB, which is not high but assumable.
Figure 3-23 IF limiter amplifier post-layout simulation gain results
TABLE 3-8 IF amplifier and filter performance
|
Spec. |
Post-layout |
Unit |
|
|
G |
 |
85 |
dB |
|
BW |
6 |
5.2 |
MHz |
|
Current |
3 |
2.4 |
mA |
Analogue-to-Digital Conversion (ADC)
As mentioned in the previous topic, the 20.42MHz down-converted signal is subsampled at a sampling rate of 16.368MHz, down-converting the incoming signal to a second IF of 4.092MHz.
The employed sampling rate, quantisation, and precorrelation bandwidth are all related and have a combined effect on the implementation losses in the receiver. These effects differ, depending on whether the signal is corrupted by Gaussian noise, other types of interference, or both. As mentioned in the previous topic, in the presence of Gaussian noise, the degradation caused by quantisation depends on the precor-relation bandwidth and the number of bits. For an optimum ratio of maximum threshold to RMS noise level, the number of bits should be as high as possible and the degradation caused by quantisation as low as possible. For a precorrelation bandwidth of five times the chipping rate (1.023MHz) and an analogue-to-digital converter of >3bits, the typical degradation is below 0.5dB.
However, as mentioned in the previous topic, a 1bit quantisation has been selected even when higher-degradation was introduced. This allows for the design of a simpler, lower-power receiver without the need for automatic gain control. As the IF frequency is relative low with a period of approximately 50ns, the complementary metal oxide semiconductor (CMOS) A/D aperture time poses no problem. The 1bit A/D converter has been implemented using a latch, as can be seen in Figure 3-24.
The operation of the latch can be divided into two stages: comparison and data storage. During data storage or the noncomparison stage (clock 3.3V), M6 and M7 transistors behave like short circuits, allowing the input signal to be stored in the C1 and C2 capacitors. In addition, the positive feedback loop is disabled by means of M5. For the comparison stage (clock 0V), M5, M6, and M7 transistors are open circuit, resulting in isolated input and an activated positive feedback loop. The differential voltage stored in the previous stage biases M3 and M4 transistors.
Figure 3-24 Latch comparator
M3 and M4 will drive current in an uneven way, dictated by the charge stored in C1 and C2. This will unbalance the nodes Out+ and Out-. The positive feedback loop will set the outputs to VDD or GND, depending on the case. Figure 3-25 shows voltage stored in the capacitors and the amplifier output signals.
Layout Considerations and Simulation Results
The main component of the ADC is the latch, as shown in the previous section. Figure 3-24 shows the circuit diagram for the latch composed of two 765fF capacitors and seven transistors, the sizes of which are shown in Table 3-9. The layout of the ADC is shown in Figure 3-26.
Figure 3-25 Time response of the latch
TABLE 3-9 Size of latch amplifier transistors
|
Transistors |
Width (W) |
Length (L) |
Unit |
 |
8 |
1 |
 |
 |
3 |
0.35 |
 |
 |
2 |
0.35 |
 |
Figure 3-26 Layout of the ADC
TABLE 3-10 Consumption, operation frequency, and offset of the ADC
|
Consumption |
Operation Frequency |
Offset voltage |
|
1.5mW |
16.368MHz |
± 12.5mV |
Table 3-10 shows the current consumption, the operating frequency, and the ADC input offset voltage. While the first two have been obtained from simple post-layout simulations, the offset has been obtained through a Montecarlo analysis of 200 samples (Figure 3-27).
To see the importance of metastability errors, time response simulations of different input signals have been carried out. The results show that no metastability problems arise with the working frequency (~20MHz).
Due to the nature of the latch amplifier, the signal at the output is correct only 50 percent of the time. To provide a constant valid output signal, a flip-flop is placed at the output of the latch. The flip-flop provides a single output synchronised with a clock from the two outputs of the latch amplifier. Figure 3-28 shows the circuit diagram for the flip-flop, which consists of logical gates.
