GPS & Galileo – Dual RF Front-end Receiver and Design, Fabrication, and Test

Circuit Design (GPS) Part 2

Layout Considerations and Simulation Results Figure 3-9 shows a microphotograph of the designed dual-gain LNA. The emitter-degenerating inductances, the power supply decoupling capacitors, and the amplifier connection pads can be clearly identified. The VDD decoupling capacitors filter out any bias noise and help improve LNA stability, which is of concern due to capacitive and bondwire […]

Circuit Design (GPS) Part 3

Combined RF Pre-Amplifier and Mixer Design As previously explained, a relatively high-gain receiver configuration has been chosen. For this reason, the RF mixer has been implemented using a differential input amplifier plus a Gilbert cell. Figure 3-15 shows the final simplified circuit diagram. Taking previous design considerations into account, the input impedance of the Gilbert […]

Circuit Design (GPS) Part 4

Layout Considerations and Simulation Results Figure 3-22 shows the layout of the IF amplifier. Common centroid techniques and dummy structures have been employed to minimise any imbalance in the differential path. TABLE 3-6 Size of the transistors and load resistor values for the first stage of the IF amplifier Transistor Resistor TABLE 3-7 Values of […]

Circuit Design (GPS) Part 5

Frequency Synthesiser The frequency synthesiser has been implemented by means of a PLL. The simplified block diagram of which is shown in Figure 3-29. The feedback loop causes both input signals of the phase frequency detector (PFD), the output of the pierce oscillator, and the output of the pulse swallow divider to lock, thereby creating […]

Circuit Design (GPS) Part 6

Pulse Swallow Divider To compare the VCO output signal frequency with the reference Xtal frequency, a divider is required. For the design example, it consists of a dual modulus prescaler (N = 4, (N+1)/N), a program counter (P = 20), and a swallow counter (S = 15/16) (see Figure 3-33). Therefore, from Eq. 3-38 [Razavi97], […]

Circuit Design (GPS) Part 7

Phase Frequency Detector and Charge Pump The output of an ideal PFD and charge pump is a current linearly proportional to the phase difference of the inputs, that is, the Xtal reference and the PLL feedback loop signal. Eq. 3-39 predicts the ideal behaviour of the PFD and charge pump illustrated in Figure 3-42.   […]

Circuit Design (GPS) Part 8

Loop Filter The use of passive filters over active filters in today’s high-performance digital PLL is recommended due to passive filters’ lower noise and complexity. The basic passive filter configuration for a current mode charge pump PLL, such as the one described in the previous sections, is shown in Figure 3-51(a). The loop filter is […]

Circuit Design (GPS) Part 9

Floor Planning and Chip Layout Considerations Figure 3-53 shows the microphotograph of the entire RF front-end chip. The chip size is approximately 2800x3000pm2 and it is a PAD-limited design. Due to the high frequency of the incoming signal, many layout issues may affect the performance of the receiver. These may include, for example, coupling through […]

Measurements (GPS) Part 1

Once the design and fabrication of the receiver have been carried out, validation is required. This topic deals initially with the characterisation of the blocks and finally with the measurement of the whole front-end. The different test setups used are described with this objective in mind. Moreover, the required printed circuit board (PCB) and external […]

Measurements (GPS) Part 2

LNA Measurement The LNA has been measured on the PCB from the packaged IC with the configuration shown in Figure 4-6(b). This is possible because the LNA is connected to the external SAW, making the input and the output directly available through the IC pins, as shown in Figure 4-4. The packaged LNA has been […]