Optimizing Capacitance and Switching Activity to Reduce Dynamic Power - Computer Architecture Techniques for Power-Efficiency - page 51

Bit-line segmentation : This technique reduces the apparent capacitance of a long bit-
line, as seen by the memory cells and the peripheral circuitry (precharge circuits and
sense amps). The net effect is that for the same cache activity, less capacitance is
switched. This technique is further described in “Sidebar: Bit-line Segmentation”.
4.2 IDLE-UNIT SWITCHING ACTIVITY: CLOCK GATING
The techniques presented in this section aim to reduce or eliminate excess activity that does
not have any effect on the computation being performed. This type of excess activity appears
at different granularities: from the tiniest circuits and individual flip-flops, to whole functional
units, or even larger structures and whole subsystems (e.g., memory, I/O, CPU). Idle-unit
switching activity is caused by the clock being fed to an idle unit —at any of the granularities
mentioned above—which, for that particular time, does nothing useful with respect to the
computation being performed.
Clock gating : Gating the clock to the particular idle unit using a control signal is the way
to eliminate such a switching activity. Clock gating is the central mechanism used in many of the
techniques and policies that we discuss later in this chapter. However, we make a distinction
between the mechanism of clock gating and the high-level policies that make use of this
mechanism at various granularities. Higher-level policies are described according to the type
of excess activity they were destined for. For instance, the following two applications of clock
gating are not simply lumped under the current heading but are explained elsewhere.
Value gating , which is presented in Section 4.3, has to do with the unused width in the
datapath in the presence of narrow-width operands.
Pipeline balancing, which is presented in Section 4.5, is a way to adjust the issue width
of an out-of-order microarchitecture to fit program needs.
In both of these examples, it is the high-level policy which engages clock gating that is
of interest and not the clock gating mechanism per se . In this section, we concentrate solely on
the mechanism of clock gating as it applies to basic circuits, to larger logic blocks, and finally
to the processor core.
4.2.1 Circuit-Level Basics
At the granularity of a small circuit or an individual flip-flop, clock gating reduces power
by preventing unnecessary charging and discharging of the circuit's capacitances [ 152 ]. For a
flip-flop, the capacitance of interest is the cumulative capacitance connected to the clock. This
capacitance, shown as C g in Figure 4.1, is charged and discharged in every clock cycle. Using
an AND gate to gate the clock with a control signal, we replace the capacitance of the flip-flop
with the capacitance of the AND gate when the control signal is 0: the AND gate transistors