Optimizing Capacitance and Switching Activity to Reduce Dynamic Power - Computer Architecture Techniques for Power-Efficiency - page 52

clk Out

data out

C g

clk

In

Pull-Down
Logic

C L

C g

data out

Out

clk

clk

ctrl

ctrl

In

C g Pull-Down

Logic

C L

C g

FIGURE 4.1: Clock gating in flip-flops and dynamic cells.

switch with the clock, but the flip-flop transistors do not. Since the capacitance of the gate is
much smaller than that of the flip-flop, power is saved.
For logic we distinguish two cases: static and dynamic (domino) logic. For static logic,
to eliminate any switching it is enough to prevent the inputs from changing. Usually, this
can be accomplished by clock gating the input latches (or flip-flops). However, in the case of
dynamic logic, which constitutes the bulk of the high-performance logic in a processor, things
are different. Power can be consumed even if the inputs to the circuit do not change .Indynamic
logic, the output is precharged to V dd and a pull-down network can discharge the output
node to Gnd if needed. So, if the logic function implemented by the circuit evaluates to 0, its
output node will be charged and discharged in every cycle, even with constant inputs. Thus,
in a dynamic logic cell, besides the capacitance connected to the clock ( C g ), its own output
capacitive load ( C L ) comes into play and can switched (precharged and discharged) every
cycle.

At this granularity, clock-gating can be applied at the Register Transfer Level (RTL)
with simple transformations on the unoptimized designs. For example, in flip-flops where the
input is guarded by a condition, this condition can be used to gate the clock instead (Figure 4.2,
left side). When such a flip-flop is part of a pipeline, the same condition can be propagated to
gate subsequent stages (Figure 4.2, right side) using additional latches that are always clocked.
Because additional hardware is required for clock gating, the benefit should be large enough to
warrant it. Today, such transformations are routinely applied by all major RTL compilers. In
contrast, at coarser granularities, high-level control policies are needed to decide when to gate
the clock to whole blocks.