Optimizing Capacitance and Switching Activity to Reduce Dynamic Power - Computer Architecture Techniques for Power-Efficiency - page 50

size of structures, via locality, or by breaking up larger monolithic structures into smaller
chunks.
While the total capacitance of a chip depends on both the capacitance of its transistors
and the capacitance of its wires, the latter becomes increasingly important with every process
generation. The dynamic power formula actually describes the power expended by charging
and discharging the node capacitance at the output of every logic gate. Burd and Brodersen
[ 39 ] describe this capacitance, C L ,as: C L C Fixed .

The first term, C W , is the product of a technology constant and the device width, W .
For a single node, C W consists of the input capacitance of the subsequent gates plus some of
the diffusion capacitance of the node's output. Although there is a significant control over the
device width W , its optimization becomes a complex interplay between power and delay which
is best handled at the cicruit level.
Architecture, on the other hand, largely determines the number of nodes required in a
design (e.g., structure sizes) and their fan-out. Some low-power architectural techniques aim to
reduce the total effective capacitance by adding more hardware which raises the total capacitance.
The goal in this case is to reduce the overall switching activity enough to produce net gains in
power consumption.
The true playground for the architect is the second term, C Fixed , which is composed
of the remaining part of the diffusion capacitance of the gate's output (not dependent on
W ) and the capacitance of the (wire) interconnect connecting the gate's output to the inputs
of subsequent gates. Wire capacitance can be reduced by effective placement and routing,
but also by architectural choices. More importantly, reducing wire capacitance yields benefits
simultaneously in power and speed (latency).
Wire capacitance directly affects lanetcy which is determined by the wire's R

= C W +

C product.
Architectural techniques to aleviate latency (for example, clustered functional unit organiza-
tions, multiscalar-like architectures [ 209 ], NUCA caches [ 140 ], tiled CMPs, etc.) also affect
C . Consider, for instance, that a non-uniform cache architecture (NUCA) breaks up large
monolithic memory banks into smaller chunks to address long wire latencies found in bit-lines
and wordlines. In the process, however, this changes the effective capacitance of the cache.
Besides large-scale architect ural choices that enhance locality (i.e., promote the use
of shorter wires), many low-power architetcural techniques require the partitioning of large
structures into smaller segments. Such techniques are commonly based on two circuit-level
techniques that affect wire-capacitance: wire partitioning and bit-line segmentation .

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Wire partitioning : This technique breaks up long wires in order to reduce their wire
delay. The resultant segmented wire can be shortened by electrically “turning off” part
of it. This eliminates switching in the disabled part, and reduces the capacitance of the
active part (see “Sidebar: Wire Partitioning”).