Optimizing Capacitance and Switching Activity to Reduce Dynamic Power - Computer Architecture Techniques for Power-Efficiency - page 48

description of the prevailing line of attack (column four), and example techniques used to
eliminate this type of switching activity (column five). Here, we describe each of the seven
activity types in more detail.
Idle-Unit Switching Activity : This is excess switching activity triggered by clock tran-
sitions in otherwise unused portions of the hardware. The classic example of this type
is an ALU adder that switches every single clock cycle even when it is not producing
any useful results. The straightforward solution is to gate the clock to the whole unit
(Section 4.2).
Idle-width switching activity 1 : This type of activity is the result of a mismatch in
the implemented width of various processor structures (datapaths, ALUs, register files,
caches) and the actual width used in many common operations. For example, operating
on 8-bit quantities in 32-bit hardware entails unnecessary switching simply because the
original design is wider than what is actually needed for such operations. The solution
is to dynamically adjust the hardware to narrow width operands . Techniques dealing with
this type of activity encompass datapaths, sequential logic (Section 4.3), and caches
(Section 4.4). Value compression also falls in this category, considering compressed
values as a special case of narrow-width values (since all the significant information is
carried with fewer bits).
Idle-capacity switching activity 1 : Another type of “over-provisioned” activity results
when a program does not use the provided hardware structures in their entirety. This
is not to say that the original design is over-provisioned in all cases. In fact, processor
structures are finely (and laboriously) balanced to provide peak performance for target
workloads. Rather, the wording is meant to stress that sometimes there is a mismatch
between what is offered and what is needed and this creates opportunities for dynamic
capacity optimizations. Idle-capacity switching activity is especially evident in large
CAM structures (e.g., instruction queues), where searching entails activity proportional
to size. Again, this type of activity can be avoided by resizing structures to match program
behavior (Section 4.5). Often, dynamic resizing also affects capacitance requiring the
segmentation of long wires into smaller segments. Relevant techniques for reducing
the switching activity of the instruction window hardware, the core (as a whole) and
the caches are presented in Sections 4.6, 4.7, and 4.8, respectively.
1 Idle-unit ,and idle-width/idle-capacity are similar to some degree—useless activity that can be eliminated—but a
distinction is made so that the first ( unit ) concerns excess activity in whole units or structures and the last two
( width and capacity ) concern excess activity in slices across units or structures. The distinction is subtle and has to do
with program behavior: idle-unit switching activity has to do with what resources the program does not use in their
entirety ; idle-width or idle-capacity switching has to do with partial use of resources.