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Parallel switching activity : Significant activity is also expended in parallel for
performance. An example is the parallel search of all the ways of an associative cache
while it is known beforehand that all but one—at most—will fail to produce a hit
(Section 4.9). Another example is the parallel activity in snoopy caches that keeps them
coherent. Some of this parallel switching activity can be eliminated at the expense of
some performance . In contrast to unnecessary or over-provisioned activity which, theoreti-
cally, can be eliminated without an impact on performance, reducing parallel switching
activity requires sophisticated schemes that trade performance for power (Section 4.9).
Cacheable switching activity: Repetitive switching activity can be avoided if it relates
to operations whose results can be cached and reused. The repetitive nature of this
switching activity is due to program locality. Once we recognize such behavior, we
can convert computing activity to cache lookups , which are designed to use less power
on average (Section 4.10). A real-world example are the trace caches in the Intel
P6 architecture, which are intended to avoid expensive decoding/uop translation of
frequently reappearing IA-32 instructions. Caching cache operations (reads and writes)
lead to techniques such as filter caches or loop buffers (Section 4.10).
Speculative switching activity : This type of activity is unique to out-of-order proces-
sors supporting speculative execution. Speculatively executing incorrect instructions
is wasted activity. The line of attack here is to throttle speculative execution when the
confidence for its usefulness is low (Section 4.11).
Value-dependent switching activity : Power consumed in this case depends on the actual
data values. Thus, a different encoding of the data can potentially reduce power con-
sumption. Although switching activity in circuits largely depends on their inputs (e.g.,
the switching activity of an adder depends on what it adds), one of the most successful
areas for applying data encodings is data communication. The prime example is bus
switching activity where power is consumed only if bus lines are switched to different
logic values (Section 4.12). In this case, a different data encoding can reduce bus line
transitions.
4.1.2 Capacitance
The total capacitance of a chip, C , does not change dynamically; it is fixed at design time.
Architecture, microarchitecture, and circuit design, however, do influence the magnitude of
C by dictating both the total number of transistors and their interconnect. In an imple-
mentation, floorplanning and place-and-route methodologies also play a significant role in
determining C , affecting the actual length of the wires on chip, but we do not examine
them here. We limit our discussions on how architecture affects C —for example: via the
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