Information Technology Reference
In-Depth Information
TABLE 4.1:
Types of switching activities that can be reduced to save power. An additional
Line of Attack
that can potentially apply to
many types of switching activity and different granularities is
Dynamic Work Steering
, presented separately in
Section 4.13
Excess
Switching
Activity
Cause
Granularity
Line of Attack
Example Technique
Section
Idle-unit
Clock-induced switching
in unused (idle) units
Functional unit
Clock gating
Clock-gated Functional Units
[
11
,
218
,
152
,
57
,
58
]
4.2
Idle-width
Bit-width too wide for
typical operations
Cross section of FUs,
datapaths, caches
Adapting to
narrow-width
operands
Clock-gated high-order bits in
ALUs [
37
,
44
], cache
compression
[
221
,
235
,
234
,
237
,
141
]
4.3, 4.4
Idle-capacity
Processor structures sized
to support peak ILP
not fully utilized in
typical programs
Large processor
structures: instruction
queues, core width,
caches
Dynamic resizing
instruction queue resizing
[
42
,
80
,
182
], cache resizing
[
244
,
8
,
21
,
68
,
9
,
168
,
241
,
131
]
4.5,4.6,
4.7, 4.8
Parallel-
speculative
Parallel (speculative)
activity for speed
Caches, coherence H/W
Serializing or filtering
parallel activity
Way prediction and other
techniques for set-associative
caches [
95
,
87
,
133
,
109
,
183
,
242
,
249
,
168
,
241
,
131
]
Coherence, [
171
]
4.9
Cacheable
(repetitive)
Repetitive computing
with the same inputs,
or repetitive memory
accessing
Architectural structures:
FUs, caches
Caching—or
memoization
Work reuse [
56
,
86
,
107
,
208
],
filter cache [
142
], loop buffers
[
150
,
24
,
25
,
232
,
10
,
110
],
trace caches [
193
,
210
]
4.10
Speculative
Activity wasted on
wrong speculation
Out-of-order core
Execution throttling
Pipeline & selective gating
[
161
,
16
]
4.11
Value-dependent
Data value encoding
not optimal
FU, datapaths
Applying different
data encoding
Bus encodings [
176
,
75
,
27
,
28
,
173
,
212
,
26
,
188
,
55
,
233
]
4.12
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