Managing Static (Leakage) Power - Computer Architecture Techniques for Power-Efficiency - page 138

5.2 ARCHITECTURAL TECHNIQUES USING
THE STACKING EFFECT
Transistor stacking refers to the technique of stacking off transistors source to drain [ 240 ].
Stacked off transistors, especially if any of them are high- V T devices, significantly restrict the
leakage current flowing to ground. This is because the voltage differential between the drain
and source of the stacked transistors is less than V dd . In addition, there is a change in the V T
of the bottom transistor that also helps in reducing the leakage current. A popular stacking
technique is the gated- V dd (or gated- V ss ) technique developed by Powell et al. for memory cells
[ 184 ].

The stacking effect, and in particular its gated V dd incarnation, has been successfully
employed in many architectural techniques, such as the DRI I-cache [ 184 ] and cache decay
[ 127 ] among others. The initial target for these techniques has been the cache hierarchy. The
basic strategy is to turn off unused parts of the cache to reduce leakage. These techniques are
collectively known as non-state-preserving (or state-destroying ). This is because the underlying
mechanism destroys all state by cutting off the power supply to the target circuit. Here, we
briefly present the gated V dd mechanism and proceed with the architectural techniques that
use it.

Gated-V dd : Powell, Yang, Falsafi, Roy, and Vijaykumar proposed the circuit-level mech-
anism to reduce leakage, called gated V dd [ 184 ]. The technique is well suited for use with
six-transistor SRAM cells but can also be used in other arbitrary logic circuits.
Gated- V dd is a transistor stacking technique. Figure 5.2 shows a traditional six-transistor
SRAM cell and its gated- V dd counterpart. The difference is the sleep transistor that gates the
ground. In normal operation, the sleep transistor is on . Turning this transistor off disconnects
the SRAM cell from the power supply. While leakage currents in the “off” transistors of the cell
are virtually eliminated, the “on” transistors lose the ability to draw current from the power rail
since the path to ground is cut off. This means that the feedback loop of the memory cell cannot

V dd

V dd

bitline

bitline bitline bitline

wordline wordline

virtual Gnd

gated - V dd
control

Gnd

Gnd

FIGURE 5.2: Gated V dd six-transistor SRAM cell. Reproduced from [ 239 ]. Copyright 2001 IEEE.