Managing Static (Leakage) Power - Computer Architecture Techniques for Power-Efficiency - page 139

maintain the charge in its internal nodes. The cell quickly loses its stored value going into a
limbo state. Restoring the power supply (turning on the sleep transistor) allows the internal
nodes of the cell to recharge, but they take on a random logic state.
5.2.1 Dynamically Resized (DRI) Cache
In tandem with the gated- V dd mechanism, Powell et al. [ 184 ] and Yang et al. [ 239 ]proposed
an architectural technique to reduce leakage in instruction caches. This technique, referred to
as the Dynamically Resized ( DRI ) instruction cache, is the first of its kind—an architectural
technique to save leakage power.
The idea is to resize the instruction cache to fit just the working set of the code that is
currently running, turn off the rest of the cache (using gated- V dd sleep transistors), and save
the corresponding leakage power. The instruction cache is the obvious initial target for such
techniques because of the working set properties of code. Typically, the working set for code
exhibits high temporal locality. Consider, for example, loop behavior where for long stretches
of time only a fixed, well-defined, part of the I -cache is accessed.
The design for a direct-mapped DRI cache is shown in Figure 5.3. The design can be
easily extended to a set-associative organization. The cache is resized in its number of sets by
changing the number of index bits with the help of a “ size mask .” The mask disables any number
of high-order index bits from left to right. The number of active sets in the cache is halved each
time an index bit is disabled. To accommodate a varying index size, the tags are extended to
also store the maximum number of index bits that could be disabled. Thus, the tags increase in
size by the corresponding amount.
FIGURE 5.3: DRI cache. Reproduced from [ 239 ]. Copyright 2001 IEEE.