Civil Engineering Reference
In-Depth Information
[ABZV03b]
A. Agarwal‚ D. Blaauw‚ V. Zolotov‚ and S. Vrudhula. Statistical
timing analysis using bounds. In
Proceedings of Design‚ Automa-
tion and Test in Europe Conference‚
pages 62-67‚ February 2003.
C. Amin‚ M. H. Chowdhury‚ and Y. I. Ismail. Realizable RLCK
circuit crunching. In
Proceedings of the ACM/IEEE Design Au-
tomation Conference‚
pages 226-231‚ 2003.
[ACI03]
[ADK01]
C. J. Alpert‚ A. Devgan‚ and C. V. Kashyap. RC delay metrics
for perforamnce optimization.
IEEE Transactions on Computer-
Aided Design of Integrated Circuits and Systems‚
20(5):571-582‚
May 2001.
[ADP02]
E. Acar‚ F. Dartu‚ and L. T. Pileggi. TETA: Transistor-level
waveform evaluation for timing analysis.
IEEE Transactions
on Computer-Aided Design of Integrated Circuits and Systems‚
21(5):605-616‚ May 2002.
[ADQ98]
C. J. Alpert‚ A. Devgan‚ and S. T. Quay. Buffer insertion for noise
and delay optimization. In
Proceedings of the ACM/IEEE Design
Automation Conference‚
pages 362-367‚ 1998.
[ADQ99]
C. J. Alpert‚ A. Devgan‚ and S. T. Quay. Buffer insertion with
accurate gate and interconnect delay computation. In
Proceedings
of the ACM/IEEE Design Automation Conference‚
pages 479-484‚
1999.
H. L. Abdel-Malek and A.-K. S. O. Hassan. The ellipsoidal tech-
nique for design centering and region approximation.
IEEE Trans-
actions on Computer-Aided Design of Integrated Circuits and Sys-
tems‚
10(8):1006-1014‚ August 1991.
[AMH91]
[AMO93]
R. K. Ahuja‚ T. L. Magnanti‚ and J. B. Orlin.
Network Flows
Theory‚ Algorithms and Applications.
Prentice Hall‚ Englewood
Cliffs‚ NJ‚ 1993.
[ARP00]
R. Arunachalam‚ K. Rajagopal‚ and L. T. Pileggi. TACO: Timing
Analysis with COupling. In
Proceedings of the ACM/IEEE Design
Automation Conference‚
pages 266-269‚ 2000.
[ASB03]
K. Agarwal‚ D. Sylvester‚ and D. Blaauw. An effective capacitance
based driver output model for on-chip RLC interconnects. In
Proceedings of the ACM/IEEE Design Automation Conference‚
pages 376-381‚ 2003.
[AZB03]
A. Agarwal‚ V. Zolotov‚ and D. T. Blaauw. Statistical timing anal-
ysis using bounds and selective enumeration.
IEEE Transactions
on Computer-Aided Design of Integrated Circuits and Systems‚
22(9):1243-1260‚ September 2003.
