Civil Engineering Reference
In-Depth Information
D. W. Bailey and B. J. Benschneider. Clocking design and analysis
for a 600-MHz Alpha microprocessor. IEEE Journal of Solid-State
Circuits‚ 33(11):1627-1633‚ November 1998.
[BB98]
M. R. Becer‚ D. Blaauw‚ I. Algolu‚ R. Panda‚ C. Oh‚ and I. N. Hajj
V. Zolotov. Post-route gate sizing for crosstalk noise reduction.
In Proceedings of the ACM/IEEE Design Automation Conference‚
pages 954-957‚ 2003.
[BC96]
A. Balakrishnan and S. Chakradhar. Retiming with logic dupli-
cation transformation: Theory and an application to partial scan.
In Proceedings of the International Conference on VLSI Design‚
pages 296-302‚ 1996.
K. P. Belkhale. Timing analysis with known false sub-graphs.
In Proceedings of the IEEE/ACM International Conference on
Computer-Aided Design‚ pages 736-740‚ 1995.
[Bel95]
[Ber97]
M. Berkelaar. Statistical delay calculation‚ a linear time method.
In Proceedings of ACM/IEEE International Workshop on Tim-
ing Issues in the Specification and Synthesis of Digital Systems
(TAU)‚ pages 15-24‚ December 1997.
M. R. C. M. Berkelaar and J. A. G. Jess. Gate sizing in MOS
digital circuits with linear programming. In Proceedings of the
European Design Automation Conference‚ pages 217-221‚ 1990.
[BJ90]
M. S. Bazaraa‚ J. J. Javis‚ and H.D. Sherali. Linear Programming
and Network Flows. John Wiley‚ New York‚ NY‚ 1977.
[BJS77]
K. D. Boese and A. B. Kahng. Zero-skew clock routing trees with
minimum wirelength. In Proceedings of the IEEE International
ASIC Conference‚ pages 17-21‚ 1992.
[BK92]
J. Baumgartner and A. Kuehlmann. Min-area retiming on flexible
circuit structures. In Proceedings of the IEEE/ACM International
Conference on Computer-Aided Design‚ pages 176-182‚ 2001.
[BK01]
K. Boese‚ A. Kahng‚ B. McCoy‚ and G. Robins. Near-optimal
critical sink routing tree constructions. IEEE Transactions
on Computer-Aided Design of Integrated Circuits and Systems‚
14(12):1417-1436‚ December 1995.
[BKMR95]
M. Borah‚ R. M. Owens‚ and M. J. Irwin. Transistor sizing for low
power CMOS circuits. IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems‚ 15(6):665-671‚ June
1996.
[BOI96]
Search WWH ::




Custom Search