Civil Engineering Reference
In-Depth Information
[AB98]
H. Arts and M. Berkelaar. Combining logic synthesis and retiming.
In Workshop Notes‚ International Workshop on Logic Synthesis‚
pages 136-139‚ 1998.
[ABP01]
R. Arunachalam‚ R. D. Blanton‚ and L. T. Pileggi. False cou-
pling interactions in static timing analysis. In Proceedings of the
ACM/IEEE Design Automation Conference‚ pages 726-731‚ 2001.
A. Agarwal‚ D. Blaauw‚ V. Zolotov‚ S. Sundareswaran‚ M. Zhao‚
K. Gala‚ and R Panda. Path-based statistical timing analy-
sis considering inter- and intra-die correlations. In Proceedings
of ACM/IEEE International Workshop on Timing Issues in the
Specification and Synthesis of Digital Systems (TAU)‚ pages 16-
21‚ December 2002.
[ABZ03a]
A. Agarwal‚ D. Blaauw‚ and V. Zolotov. Statistical clock skew
analysis considering intra-die process variations. In Proceedings
of the IEEE/ACM International Conference on Computer-Aided
Design‚ pages 914-921‚ 2003.
A. Agarwal‚ D. Blaauw‚ and V. Zolotov. Statistical timing analysis
for intra-die process variations with spatial corelations. In Proceed-
ings of the IEEE/ACM International Conference on Computer-
Aided Design‚ pages 900-906‚ November 2003.
[ABZ03b]
A. Agarwal‚ D. Blaauw‚ V. Zolotov‚ S. Sundareswaran‚ M. Zhao‚
K. Gala‚ and R. Panda. Statistical timing analysis considering
spatial correlations. In Proceedings of the Asia/South Pacific De-
sign Automation Conference‚ pages 271-276‚ January 2003.
[ABZV03a]
A. Agarwal‚ D. Blaauw‚ V. Zolotov‚ and S. Vrudhula. Compu-
tation and refinement of statistical bounds on circuit delay. In
Proceedings of the ACM/IEEE Design Automation Conference‚
pages 348-353‚ June 2003.
Search WWH ::




Custom Search