STATISTICAL STATIC TIMING ANALYSIS - Timing - page 114

shown in Figure 6.1(b). This may conservatively be captured in the form of
process corners at which the circuit is simulated.
Although it is conceptually possible to model the shape of the feasible region‚
a large amount of related prior work in the analog context [DH77‚ AMH91‚
SVK94] has shown that such approaches can handle problems of only limited
dimensionality. This is also borne out by the work in in the context

of digital circuits.
In nanometer technologies‚ intra-die variations have become significant and
can no longer be ignored. As a result‚ a process corner based methodology‚
which would simulate the entire chip at a small number of design corners‚ is
no longer sustainable. A true picture of the variations would use one process
corner in each region of the chip‚ but it is clear that the number of simulations
would increase exponentially with the number of such regions. This implies
that if a small number of process corners are to be chosen‚ they must be very
conservative and pessimistic. For true accuracy‚ this can be overcome by using
a larger number of process corners‚ but this number may be too large to permit
computational efficiency.
Our discussion in this chapter will focus primarily on intra-die variations.
Unlike inter-die variations‚ whose effects can be captured by a small number of
static timing analysis (STA) runs at the process corners‚ a more sophisticated
approach is called for in dealing with intra-die variations. This requires an
extension of traditional STA techniques to move beyond their deterministic na-
ture. An alternative approach that overcomes these problems is statistical STA
(SSTA)‚ which treats delays not as fixed numbers‚ but as probability density
functions (PDF's)‚ taking the statistical distribution of parametric variations
into consideration while analyzing the circuit.
The sources of these variations may be used to create another taxonomy:
Random variations (as the name implies) depict random behavior that can
be characterized in terms of a distribution. This distribution may either be
explicit‚ in terms of a large number of samples provided from fabrication line
measurements‚ or implicit‚ in terms of a known probability density function
(such as a Gaussian or a lognormal distribution) that has been fitted to
the measurements. Random variations in some process or environmental
parameters (such as those in the temperature‚ supply voltage‚ or can
often show some degree of local spatial correlation‚ whereby variations in
one transistor in a chip are remarkably similar in nature to those in spatially
neighboring transistors‚ but may differ significantly from those that are far
away. Other process parameters (such as and do not show much
spatial correlation at all‚ so that for all practical purposes‚ variations in
neighboring transistors are uncorrelated.
Systematic variations show predictable variational trends across a chip‚ and
are caused by known physical phenomena during manufacturing. Strictly
speaking‚ environmental changes are entirely predictable‚ but practically‚
due to the fact that these may change under a large number (potentially
exponential in the number of inputs and internal states) of operating modes