Civil Engineering Reference
In-Depth Information
Inter-die variations
are the variations from die to die‚ and affect all the de-
vices on same chip in the same way‚ e.g.‚ they may cause all of the transistor
gate lengths of devices on the same chip to be larger or all of them to be
smaller.
Intra-die variations
correspond to variability within a single chip‚ and may
affect different devices differently on the same chip‚ e.g.‚ they may result
in some devices having smaller oxide thicknesses than the nominal‚ while
others may have larger oxide thicknesses.
Inter-die variations have been a longstanding design issue‚ and for several
decades‚ designers have striven to make their circuits robust under the unpre-
dictability of such variations. This has typically been achieved by simulating
the design at not just one design point‚ but at multiple “corners.” These corners
are chosen to encapsulate the behavior of the circuit under worst-case varia-
tions‚ and have served designers well in the past. In nanometer technologies‚
designs are increasingly subjected to numerous sources of variation‚ and these
variations are too complex to capture within a small set of process corners.
To illustrate this‚ consider the design of a typical circuit. The specifications
on the circuit are in the form of limits on performance parameters‚ such
as the delay or the static or dynamic power dissipation‚ which are dependent
on a set of design or process parameters‚ such as the transistor width or
the oxide thickness. In Figure 6.1 (a)‚ we show the behavior of a representative
circuit in the performance space of parameters‚ whose permissible range of
variations lies within a range of for each parameter‚ which
corresponds to a rectangular region. However‚ in the original space of design
parameters‚
this may translate into a much more complex geometry‚ as
