Civil Engineering Reference
In-Depth Information
6
STATISTICAL STATIC TIMING
ANALYSIS
6.1
INTRODUCTION
Under true operating conditions‚ the parameters chosen by the circuit designer
are perturbed from their nominal values due to various types of variations. As
a consequence‚ a single SPICE-level transistor or interconnect model (or an
abstraction thereof) is seldom an adequate predictor of the exact behavior of a
circuit. These sources of variation can broadly be categorized into two classes
Process variations
result from perturbations in the fabrication process‚ due
to which the nominal values of parameters such as the effective channel
length
the oxide thickness
the dopant concentration
the
transistor width
the interlayer dielectric (ILD) thickness
and
the interconnect height and width
respectively).
Environmental variations
arise due to changes in the operating environ-
ment of the circuit‚ such as the temperature or variations in the supply
voltage and ground) levels. There is a wide body of work on analysis
techniques to determine environmental variations‚ both for thermal issues
[CK00‚ CS03b‚ WC02‚ GS03]‚ and for supply net analysis [SS02].
Both of these types of variations can result in changes in the timing and power
characteristics of a circuit.
Process variations can also be classified into the following categories:
