Civil Engineering Reference
In-Depth Information
of a circuit‚ it is easier to capture them in terms of random variations.
Examples of systematic‚ variations include those due to
Spatial intra-chip gate length variability,
also known as across-chip linewidt
h
variation (ACLV), which observes systematic changes in the value of
across a reticle due to effects such as changes in the stepper-
induced illumination and imaging nonuniformity clue to lens aberrations
ILD variations
due to the effects of chemical-mechanical polishing (CMP)
on metal density patterns: regions that have uniform metal densities
tend to have more uniform ILD thicknesses than regions that have
nonuniformities. This is illustrated by an example in Figure 6.2.
This chapter will overview the field in the area of SSTA in the presence
of intra-die variations. For simplicity‚ many of these methods assume either a
normal distribution for the gate delay‚ or a discrete probability density function
(PDF). The latter have the advantage of being more versatile in describing
on-chip variations‚ but the former can more easily capture spatial correlation
structures.
6.2 MODELING PARAMETER VARIATIONS
6.2.1
Components of variations
In general‚ the intra-chip parametric variation can be decomposed into three
parts: a deterministic global component‚
a deterministic local compo-
nent
and a random component
[LNPSOO]:
