Global Positioning System Reference
In-Depth Information
Table 5.9
Count States for 3,749th and 3,750th Cycles of X1A in Last X1 Cycle of Week
Z
X1
X1A
X1B
D1B
X2
X2A
D2A
X2B
D2B
15339838 3022
3367
0
421475
4091
0
3989
0
403199
15339839 3023
3368
0
421476
0
1069
3990
0
403199
·
·
·
·
·
·
·
·
·
·
15339941 3125
3470
0
421578
102
1069
4092
0
403199
15339942 3126
3471
0
421579
103
1069
0
965
403199
·
·
·
·
·
·
·
·
·
·
15340563 3747
4092
0
422200
724
1069
621
965
403199
15340564 3748
0
343
422201
725
1069
622
965
403199
·
·
·
·
·
·
·
·
·
·
15340907 4091
343
343
422544
1068
1069
965
965
403199
15340908
0
344
343
422545
1069
1069
966
965
403199
·
·
·
·
·
·
·
·
·
·
15343929 3021
3365
343
425566
4090
1069
3987
965
403199
15343930 3022
3366
343
425567
4091
1069
3988
965
403199
15343931 3023
3367
343
425568
4091
1068
3989
965
403199
·
·
·
·
·
·
·
·
·
·
15344033 3125
3469
343
425670
4091
966
4091
965
403199
15344034 3126
3470
343
425671
4091
965
4092
965
403199
15344035 3127
3471
343
425672
4091
964
4092
964
403199
·
·
·
·
·
·
·
·
·
·
15344655 3747
4091
343
426292
4091
344
4092
344
403199
15344656 3748
4092
343
426293
4091
343
4092
343
403199
15344657 3749
4092
342
426294
4091
342
4092
342
403199
·
·
·
·
·
·
·
·
·
·
15344998 4090
4092
1
426635
4091
1
4092
1
403199
15344999 4091
4092
0
426636
4091
0
4092
0
403199
00
0
0
0
0
0
0 0
0
Note:
These count states are not the PRN code states contained in the shift registers.
5.9, D1B is always set to a count of 343 chips. D2A is set to 37 and D2B is set to 380
unless it is at the end of the last X2 cycle of the week, in which case they are set to
1,069 and 965, respectively. The rule followed by the code setters is that if their
delay counter is nonzero, they hold their final states until the delay counter counts
down to zero, then they rollover to the zero (reset) states. The delay counters rule is
that if their code setters are not in the final state, they hold their delay counts until
the code setter reaches its final state, then they begin counting down. The receiver
baseband rule is that if the code setter counts to the reset state can be reached with-
out using the delay counter, the receiver baseband process adjusts the code setter to
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