Satellite Signal Acquisition, Tracking, and Data Demodulation - Understanding GPS: Principles and Applications - page 212

the appropriate value and does not set the delay counter flag. Otherwise, it sets the
appropriate delay counter flags (which instructs the code setter hardware to put the
appropriate maximum delays into the counters). This rule avoids the need for the
code setter hardware to set any other count state into the delay counters other than
their maximum delay counts.
The code setters are loaded with the timing state valid at the first epoch that the
counting process begins. As each code setter rolls over to zero, it resets its corre-
sponding code register to that register's initial code state. In addition, the X1A
divide-by-3,750 counter and the Z counter must be set to their correct states when
the X1A register is reset. Similarly, the X1B divide-by-3,749 counter, the X2A
divide-by-3,750 counter, and the X2B divide-by-3,749 counter must be set to their
correct states when their respective registers are reset by their code setters. Thus,
when all four code setters have rolled over, the code generator is synchronized to the
code accumulator. This requires approximately 500 s in the worst case.

The final step in the explanation of the P code setter operation is the algorithm
for converting the code accumulator into P code setter states and the setting of the
three flags, D1B, D2A, and D2B. The code setter timing and the rules have already
been explained. Figure 5.32 depicts the logical flow diagram that covers all P code
setter timing conditions. This diagram should be compared to the count states in
Tables 5.7 and 5.9. Note that if the P code generator is already synchronized to the
code accumulator, the action of the P code setter does not alter the replica code state,
since the reset pulses occur at exactly the same times that they naturally occur in the
code generator. However, to ensure that the receiver baseband software code accu-
mulator always matches the P code generator code state, it is prudent for the soft-
ware to periodically repeat the code setup process.
Alternatively, all 4,092 PRN states of the 12-bit X1A and X1B shift registers
and all 4,093 PRN states of the 12-bit X2A and X2B shift registers can be
precomputed and stored as lookup tables that are indexed by the delays computed in
Figure 5.32 (without the need for the flag setting logic). These PRN values can then
be transferred to buffer code setter registers and their contents transferred into their
respective registers at the appropriate epoch.
With Y code operation, the same P code processes are implemented in the same
manner and then encrypted by a specialized hardware design. In the original mili-
tary receivers, this was called the AOC. The AOC output, when combined with P
code, synthesizes the Y code function before correlation with the incoming SV Y
code signals. The AOC implements a classified encryption algorithm, and each
receiver channel requires one AOC. The component that synchronizes all of the
AOCs to their respective replica P code generators is the PPSSM. In newer military
receivers, the AOC and the PPSSM functions are integrated into the receiver design.
The new military GPS receiver engine is the SAASM. The SAASM is a more secure
advanced military GPS receiver design. Only keyed PPS receivers can replicate the Y
code.
This code setter design example supports direct P(Y) code acquisition. Direct
P(Y) code acquisition is used if the receiver can accurately predict the satellite trans-
mit time so that less time is required to acquire the P(Y) code by direct sequence than
to perform a C/A code search and handover. The direct P(Y) code acquisition condi-
tion is satisfied if the receiver has previously acquired four or more satellites and its

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