Satellite Signal Acquisition, Tracking, and Data Demodulation - Understanding GPS: Principles and Applications - page 210

in phase). This is the only time during the GPS week that they are aligned. As can be
observed in Table 5.7, they become misaligned immediately after the first X1 cycle
of the week completes. This is because following each X1 cycle, the X2 cycle contin-
ues for an additional 37 chips. These last two cycles are chosen for the most repre-
sentative timing illustration because the X1 period is defined as 3,750 X1A cycles,
which equals 1.5 seconds or one Z count. When the X1B code reaches its last chip in
the last X1A cycle of an X1 cycle, the X1B register is held in its final state (4092) for
344 chips until the X1A register reaches its final state. Then X1A and X1B are reset.
The Z count is incremented by one, and the X1 cycle starts over.
The X2 period is defined by 3,750 X2A cycles plus 37 chips. In the last X2A
cycle of the X2 cycle, the X2B register is held in its final state (4092) until X2A
reaches its final state, and then the X2A register is held in its final state (4091) and
the X2B register continues to be held in its final state (4092) for an additional 37
chips. During this last X2A cycle, X2B is held in it final state (4092) for a total of
381 chips. Then X2A and X2B are reset and their cycles start over. Thus, the X2
epochs are delayed by 37 chips per Z count, with respect to the X1 epochs, until the
end of the GPS week.
Note in Table 5.7 that the values for the X1A, X1B, X2A, and X2B registers are
their count states, not their PRN code states. The PRN code states corresponding to
the last two count states and the reset states are shown in Table 5.8. The only PRN
code states that are important to the P code setters are the reset states, but the last
two PRN code states prior to reset are useful for code generator verification
purposes.
The previous description for X2 is correct except for the last X1A cycle of the
GPS week shown in Table 5.9. During this last cycle, the X2A register holds in its
final state (4091) and then the X2B register holds in its final state (4092) until the
end of the last X1 cycle of the week. The X1B final state holding count is the same as
for the rest of the week (compare with Table 5.7).
The same future scheduling must be performed to accomplish the code setup
process for the P code generator as was used in the C/A code setup. The X1A and
X2A code setters count P code clock cycles from 0 to 4,091 and the X1B and X2B
code setters count from 0 to 4,092. This simplified code setter design example uses
three countdown delay counters, D1B for X1B, D2A for X2A, and D2B for X2B,
which are set by flags from the receiver baseband process at the end of an X1 or X2
cycle. Note that X1A is never delayed. It is possible to design the code setter so that
the receiver baseband process does not have to set flags, but this simplified design
example suffices to explain the principles involved. As observed in Tables 5.7 and

Table 5.8 PRN Code States Corresponding to Final Two and Reset Count States

Code Setter
States
(Decimal)

X1A Code
(Hexadecimal)

X1B Code
(Hexadecimal)

X2A Code
(Hexadecimal)

X2B Code
(Hexadecimal)

4090 892 · E49 ·

4091 124 955 C92 155

4092 · 2AA · 2AA

0 (reset) 248 554 925 554