Global Positioning System Reference
In-Depth Information
carrier loop with the code loop output. This is because, unaided, the code loop ther-
mal noise is orders of magnitude larger than the carrier loop thermal noise.
Table 5.5 summarizes four GPS receiver delay lock loop (DLL) discriminators
and their characteristics. The fourth DLL discriminator is called a coherent dot
product DLL. A more linear version can be implemented using only the
E
and
L
components, but the dot product slightly outperforms it. The coherent DLL pro-
vides superior performance when the carrier loop is in PLL. Under this condition,
there is signal plus noise in the
I
components and mostly noise in the
Q
components.
However, this high-precision DLL mode fails if there are frequent cycle slips or total
loss of phase lock because the phasor rotates, causing the signal power to be shared
in both the
I
and
Q
components, which consequently causes power loss in the coher-
ent DLL. Successful operation requires a sensitive phase lock detector and rapid
transition to the quasi-coherent DLL. All of the DLL discriminators can be normal-
ized. Normalization removes the amplitude sensitivity, which improves perfor-
mance under rapidly changing SNR conditions. Therefore, normalization helps the
DLL tracking and threshold performance to be independent of AGC performance.
However, normalization does not prevent reduction of the gain (slope) when SNR
decreases. As SNR is reduced, the DLL slope approaches zero. Since loop bandwidth
Table 5.5
Common Delay Lock Loop Discriminators
Discriminator Algorithm
Characteristics
Noncoherent early minus late envelope normalized by
E
+
L
to
1
2
−
+
where:
EI
EL
EL
remove amplitude sensitivity.
High computational load.
For 1-chip
E
−
L
correlator spacing, produces true tracking error
2
2
2
2
=
+
QLI
,
=
+
Q
within
0.5 chip of input error (in the absence of noise).
Becomes unstable (divide by zero) at
±
ES
ES
LS
LS
1.5-chip input error, but this
is well beyond code tracking threshold in the presence of noise.
±
Noncoherent early minus late power.
Moderate computational load.
For 1-chip
E
1
2
2
2
(
EL
−
)
L
correlator spacing, produces essentially the same
error performance as 0.5 (
E
−
−
L
) envelope within
±
0.5 chip of input
error (in the absence of noise).
Can be normalized with
E
2
L
2
.
1
2
Quasi-coherent dot product power.
Uses all three correlators.
Low computational load.
For 1-chip
E
[(
I
−
I
)
I
+
(
QQQ
−
)
]
ES
LS
PS
ES
LS
PS
(dot product)
1
4
−
L
correlator spacing, it produces nearly true error
[(
I
−
I
) /
I
+
(
QQQ
−
) /
]
ES
LS
PS
ES
LS
PS
output within
0.5 chip of input (in the absence of noise).
Normalized version shown second using
I
PS
2
and
Q
PS
2
, respectively.
±
(normalized with
I
P
2
and
Q
P
2
)
Coherent dot product.
Can be used only when carrier loop is in phase lock.
Low computational load.
Most accurate code measurements.
Normalized version shown second using
I
PS
2
.
1
2
(
I
−
I
)
I
(dot product)
ES
LS
PS
1
4
(
I
−
I
)
(normalized with
I
P
2
)
ES
LS
I
PS
Note:
The code loop discriminator outputs may be summed to reduce the iteration rate of the code loop filter as compared to that of the
carrier loop filter when the code loop is aided by the carrier loop. The rule-of-thumb limit is that total integration time must be less than
one-fourth the DLL bandwidth. Note that this does not increase the predetection integration time for the code loop but does reduce noise.
However the code loop NCO must be updated every time the carrier loop NCO is updated, even though the code loop filter output has not
been updated. The last code loop filter output is combined with the current value of carrier aiding.
Search WWH ::
Custom Search