Global Positioning System Reference
In-Depth Information
is roughly proportional to loop gain, loop bandwidth approaches zero at low SNR.
This results in poor DLL response to dynamic stress and can result in instability if a
third-order DLL filter is used (never used with carrier-aided code implementation).
Carrier aiding (including externally provided carrier aiding) minimizes this
problem, but the phenomena may produce unexpected DLL behavior at very low
SNR.
Figure 5.14 compares the four DLL discriminator outputs. The plots assume
1-chip spacing between the early and late correlators. This means that the 2-bit shift
register is shifted at twice the clock rate of the code generator. Also assumed is an
ideal correlation triangle (infinite bandwidth) and that there is no noise on the I and
Q measurements. For typical receiver bandwidths, the correlation peak tends to be
rounded, the ramps on either side of the peak are nonlinear, and the correlation
amplitudes at
0.5-chip from the correlation peak are slightly higher than for the
infinite bandwidth case, while the prompt correlation amplitude is slightly lower.
The normalized early minus late envelope discriminator is very popular because
its output error is linear over a 1-chip range, but the dot product power
discriminator slightly outperforms it. Some GPS receiver designs synthesize the
early minus late replica code as a combined replica signal. The benefit is that only
one complex correlator is required to generate an early minus late output. This can
be normalized with the prompt signal, but linear operation in the 1-chip range can
only be achieved with E
±
+
L normalization. This requires dedicated E and L
correlators.
To reduce the computational burden of forming the GPS signal envelopes (the
magnitude of the I and Q vectors), approximations are often used. Two of the most
popular approximations (named after their originators) are the JPL approximation
and the Robertson approximation.
Power
Dot product
Normalized coherent
Normalized E -L
1.5
1
0.5
0
0.5
1
1.5
1.5
1
0.5
0
0.5
1
1.5
True input error (chips)
Figure 5.14
Comparison of delay lock loop discriminators.
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