Satellite Signal Acquisition, Tracking, and Data Demodulation - Understanding GPS: Principles and Applications - page 170

happens, the ambiguity must be resolved again. The 180º ambiguity of the Costas
PLL can be resolved by referring to the phase detection result of the data bit demod-
ulation. If the data bit phase is normal, then the carrier Doppler phase indicated by
the Costas PLL is correct. If the data bit phase is inverted, then the carrier Doppler
phase indicated by the Costas PLL phase can be corrected by adding 180º.
Costas PLLs as well as conventional PLLs are sensitive to dynamic stress, but
they produce the most accurate velocity measurements. For a given signal power
level, Costas PLLs also provide the most error-free data demodulation in compari-
son to schemes used with FLLs. Therefore, this is the desired steady state tracking
mode of the GPS receiver carrier tracking loop. It is possible for a PLL to close in a
false phase lock mode if there is excess frequency error at the time of loop closure.
Therefore, a well-designed GPS receiver carrier tracking loop will close the loop
with a more dynamically robust FLL operated at wideband. Then it will gradually
reduce the carrier tracking loop bandwidth and transition into a wideband PLL
operation in order to systematically reduce the pull-in frequency error. Finally, it
will narrow the PLL bandwidth to the steady state mode of operation. If dynamic
stress causes the PLL to lose lock, the receiver will detect this with a sensitive phase
lock detector and transition back to the FLL. The PLL closure process is then
repeated.

5.3.3 Frequency Lock Loops
PLLs replicate the exact phase and frequency of the incoming SV (converted to IF) to
perform the carrier wipeoff function. FLLs perform the carrier wipeoff process by
replicating the approximate frequency, and they typically permit the phase to rotate
with respect to the incoming carrier signal. For this reason, they are also called auto-
matic frequency control (AFC) loops. The FLLs of GPS receivers must be insensitive
to 180º reversals in the I and Q signals. Therefore, the sample times of the I and Q
signals should not straddle the data bit transitions. During initial signal acquisition,
when the receiver does not know where the data transition boundaries are, it is usu-
ally easier to maintain frequency lock than phase lock with the SV signal while per-
forming bit synchronization. This is because the FLL discriminators are less sensitive
to situations where some of the I and Q signals do straddle the data bit transitions.
When the predetection integration times are small compared to the data bit transi-
tion intervals, fewer integrate and dump samples are corrupted, but the squaring
loss is higher. Table 5.4 summarizes several GPS receiver FLL discriminators, their
output frequency errors, and their characteristics.
Figure 5.11 compares the frequency error outputs of each of these
discriminators assuming no noise in the I PS and Q PS samples. Figure 5.11(a) illus-
trates that the frequency pull-in range with a 5-ms predetection integration time
(200-Hz bandwidth) has twice the pull-in range of Figure 5.11(b) with a 10-ms
predetection integration time (100-Hz bandwidth). Note in both figures that the
single-sided frequency pull-in ranges of the cross and ATAN2(dot, cross)
FLL discriminators are equal to half the predetection bandwidths. The (cross) ×

sign(dot) FLL discriminator frequency pull-in ranges are only one-fourth of the
predetection bandwidths. Also note that the (cross) sign(dot) and the cross FLL

discriminator outputs, whose outputs are sine functions divided by the sample time

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