Global Positioning System Reference
In-Depth Information
analog side, the Nyquist sample rate is half that of the generic A/D converter
requirement. This is a design benefit if the A/D converter speed presents a design
limitation, but this is not likely with today's technology. But two A/D converters are
required to digitize the I and Q input signals. This is a design penalty that doubles
the A/D components. A single A/D converter can be used to produce the I and Q
signals if a technique referred to as quadrature sampling (also known as
pseudosampling or IF sampling ) is employed. However, the classical phase
derotation process still requires four multiplies and two additions with no addi-
tional performance improvement. This is a phase derotation design penalty of two
additional multiplies and two adds. The generic design is therefore the preferred
carrier phase derotation scheme.
These PLL characteristics are illustrated in Figure 5.10, where the phasor, A
(the vector sum of I PS and Q PS ), tends to remain aligned with the I -axis and switches
180º during each data bit reversal.
It is straightforward to detect the bits in the SV data message stream using a
Costas PLL. The I PS samples are simply accumulated for one data bit interval, and
the sign of the result is the data bit. Since there is a 180º phase ambiguity with a
Costas PLL, the detected data bit stream may be normal or inverted. This ambiguity
is resolved during the frame synchronization process by comparing the known pre-
amble at the beginning of each subframe both ways (normal and inverted) with the
bit stream. If a match is found with the preamble pattern inverted, the bit stream is
inverted and the subframe synchronization is confirmed by parity checks on the
TLM and HOW. Otherwise, the bit stream is normal. Once the phase ambiguity is
resolved, it remains resolved until the PLL loses phase lock or slips cycles. If this
Q
φ
A
Q PS
I PS
I
I PS
Q PS
A
φ
True phase error = φ
Phase ambiguity
due to data bit transition
Figure 5.10
I , Q phasor diagram depicting true phase error between replica and incoming carrier
phase.
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