Global Positioning System Reference
In-Depth Information
Table 5.4
Common Frequency Lock Loop Discriminators
Output
Frequency Error
Discriminator Algorithm
Characteristics
cross
t
Near optimal at low SNR.
Slope proportional to signal amplitude squared
A
2
.
Least computational burden.
(
−
where:
cross
t
)
sin[(
φφ
2
−
)]
2
1
1
t
−
t
2
1
=
I
PS
1
Q
PS
2
-
I
PS
2
×
Q
PS
1
(
cross
)
×
sign dot
(
)
Decision directed.
Near optimal at high SNR.
Slope proportional to signal amplitude
A
.
Moderate computational burden
(
t
−
t
)
2
1
sin[ (
2
φφ
−
)]
2
1
where:
dot
t
−
t
2
1
=
I
PS
1
I
PS
2
+
Q
PS
1
Q
PS
2
cross
=
I
PS
1
Q
PS
2
−
I
PS
2
×
Q
PS
1
Four-quadrant arctangent.
Maximum likelihood estimator.
Optimal at high and low SNR.
Slope not signal amplitude dependent.
Highest computational burden.
Usually table lookup implementation.
ATAN
2
(
dot cross
,
)
φφ
2
−
−
1
(
t
−
t
)
t
t
2
1
2
1
Note:
Integrated and dumped prompt samples
I
PS
1
and
Q
PS
1
are the samples taken at time
t
1
, just prior to the samples
I
PS
2
and
Q
PS
2
taken
at a later time
t
2
. These two adjacent samples should be within the same data bit interval. The next pair of samples are taken starting
(
t
2
- t
1
) seconds after
t
2
(i.e., no
I
and
Q
samples are reused in the next discriminator computation).
interval (
t
2
t
1
) in seconds, are also divided by 4 to more accurately approximate the
true input frequency error. The ATAN2 (
x
,
y
) function returns the answer in radi-
ans, is converted to degrees, divided by the sample time interval (
t
2
−
t
1
) in seconds,
and is also divided by 360 to produce at its output a true representation of the input
frequency error within its pull-in range. The amplitudes of all of the discriminator
outputs are reduced (their slopes tend to flatten), and they tend to start rounding off
near the limits of their pull-in range as the noise levels increase.
The
I
,
Q
phasor diagram in Figure 5.12 depicts the change in phase,
φ
2
− φ
1
,
between two adjacent samples of
I
PS
and
Q
PS
, at times
t
1
and
t
2
. This phase change
over a fixed time interval is proportional to the frequency error in the carrier track-
ing loop. The figure also illustrates that there is no frequency ambiguity in the GPS
receiver FLL discriminator because of data transitions, provided that the adjacent
I
and
Q
samples are taken within the same data bit interval. However, it is possible
for the FLL loop to close with a false frequency lock in a high dynamic environment.
For this reason, very short predetection integration times (wider pull-in range) are
important for initial FLL loop closure. For example, if the search dwell time was 1
ms or 2 ms, then the initial predetection integration time in FLL should be the same.
Note that with a FLL, the phasor,
A
, which is the vector sum of
I
PS
and
Q
PS
, rotates
at a rate directly proportional to the frequency error (between the replica carrier
and the incoming carrier). When true frequency lock is actually achieved, the vector
stops rotating, but it may stop at any angle with respect to the
I
-axis. For this rea-
son, coherent code tracking, as will be discussed in the following section, is not pos-
sible while in FLL because it depends on the
I
components being maximum (signal
plus noise) and the
Q
components to be minimum (noise only) (i.e., in phase lock).
It is possible to demodulate the SV data bit stream in FLL by a technique called
dif-
ferential demodulation.
Because the demodulation technique involves a differentia-
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