Satellite Signal Acquisition, Tracking, and Data Demodulation - Understanding GPS: Principles and Applications - page 158

be detected and corrected by the carrier tracking loop. When the PLL is phase
locked, the I signals are maximum (signal plus noise) and the Q signals are
minimum (containing only noise).
In Figure 5.2, the I and Q signals are then correlated with early, prompt, and
late replica codes (plus code Doppler) synthesized by the code generator, a 2-bit shift
register, and the code NCO. In closed loop operation, the code NCO is controlled by
the code tracking loop in the receiver processor. In this example, the code NCO pro-
duces twice the code generator clocking rate, 2 f co , and this is fed to the clock input of
the 2-bit shift register. The code generator clocking rate, f co , that contains the nomi-
nal spreading code chip rate (plus code Doppler) is fed to the code generator. The
NCO clock, f c , should be a much higher frequency than the shift register clock, 2f co .
With this combination, the shift register produces two phase-delayed versions of the
code generator output. As a result, there are three replica code phases designated as
early ( E ), prompt ( P ), and late ( L ). E and L are typically separated in phase by 1 chip
and P is in the middle. Not shown are the controls to the code generator that permit
the receiver processor to preset the initial code tracking phase states that are
required during the code search and acquisition (or reacquisition) process.
The prompt replica code phase is aligned with the incoming SV code phase pro-
ducing maximum correlation if it is tracking the incoming SV code phase. Under this
circumstance, the early phase is aligned a fraction of a chip period early, and the late
phase is aligned the same fraction of the chip period late with respect to the incom-
ing SV code phase, and these correlators produce about half the maximum correla-
tion. Any misalignment in the replica code phase with respect to the incoming SV
code phase produces a difference in the vector magnitudes of the early and late cor-
related outputs so that the amount and direction of the phase change can be detected
and corrected by the code tracking loop.
5.2.1 Predetection Integration
Predetection is the signal processing after the IF signal has been converted to base-
band by the carrier and code stripping processes, but prior to being passed through a
signal discriminator (i.e., prior to the nonlinear signal detection process). Extensive
digital predetection integration and dump processes occur after the carrier and code
stripping processes. This causes very large numbers to accumulate, even though
the IF A/D conversion process is typically with only 1 to 3 bits of quantization reso-
lution with the carrier wipeoff process involving a matching multiplication preci-
sion and the code wipeoff process that follows usually involving only 1-bit
multiplication.
Figure 5.2 shows three complex correlators required to produce three in-phase
components, which are integrated and dumped to produce I E , I P , I L and three
quadraphase components integrated and dumped to produce Q E , Q P , Q L . The car-
rier wipeoff and code wipeoff processes must be performed at the digital IF sample
rate, which is of the order of 50 MHz for a military P(Y) code receiver (that also
operates with C/A code), 5 MHz for civil C/A code receivers that use 1-chip E - L
correlator spacing, and up to 50 MHz for civil C/A code receivers that use narrow
correlator spacing for improved multipath error performance. The integrate and
dump accumulators provide filtering and resampling at the processor baseband