Satellite Signal Acquisition, Tracking, and Data Demodulation - Understanding GPS: Principles and Applications - page 157

I E

Integrate
and dump

E

I P

Integrate
and dump
Integrate
and dump
Integrate
and dump
Integrate
and dump
Integrate
and dump

.

P I L

Digi tal
IF

I

.

SIN

L

Q E

Q

.

COS

E

Q P

SIN
map

COS
map

P Q L

Receiver
processor

.

. . .

L

E

.

P L

Code
generator

Carrier
NCO

D

2-bit shift register

C

f co 2f co

Clock f c

Code
NCO

Code-phase increment per clock cycle

Clock f c

Carrier-phase increment per clock cycle

Figure 5.2 Generic digital receiver channel block diagram.

with respect to the detected carrier of the desired SV. However, the code stripping
processes that collapse these signals to baseband have not yet been applied. There-
fore, the I and Q signals at the output of the carrier mixers are dominated by noise.
The desired SV signal remains buried in noise until the I and Q signals are collapsed
to baseband by the code stripping process that follows. The replica carrier (includ-
ing carrier Doppler) signals are synthesized by the carrier numerically controlled
oscillator (NCO) and the discrete sine and cosine mapping functions.
The code wipeoff function could have been implemented before the carrier
wipeoff function in this design, but this would increase the carrier wipeoff complex-
ity with no improvement in receiver performance. The wipeoff sequence presented
in Figure 5.2 is the least complex design.
Later, it will be shown that the NCO produces a staircase function whose
period is the desired replica carrier plus Doppler period. The sine and cosine map
functions convert each discrete amplitude of the staircase function to the corre-
sponding discrete amplitude of the respective sine and cosine functions. By produc-
ing I and Q component phases 90º apart, the resultant signal amplitude can be
computed from the vector sum of the I and Q components, and the phase angle with
respect to the I -axis can be determined from the arctangent of Q / I . In closed loop
operation, the carrier NCO is controlled by the carrier tracking loop in the receiver
processor. In phase lock loop (PLL) operation, the objective of the carrier tracking
loop is to keep the phase error between the replica carrier and the incoming SV car-
rier signals at zero. Any misalignment in the replica carrier phase with respect to the
incoming SV signal carrier phase produces a nonzero phase angle of the prompt I
and Q vector magnitude, so that the amount and direction of the phase change can