Satellite Signal Acquisition, Tracking, and Data Demodulation - Understanding GPS: Principles and Applications - page 156

tioned RF signals are then down-converted to an IF using signal mixing frequencies
from local oscillators (LOs). The LOs are derived from the reference oscillator by
the frequency synthesizer, based on the frequency plan of the receiver design. One
LO per downconverter stage is required. Two-stage down-conversion to IF is typi-
cal, but one-stage down-conversion and even direct L-band digital sampling have
also been used. However, since nearly 100 dB of signal gain is required prior to
digitization, placing all of this gain at L-band is conducive to self-jamming in the
receiver front end, so downconversion is assumed here. The LO signal mixing pro-
cess generates both upper and lower sidebands of the SV signals, so the lower side-
bands are selected and the upper sidebands and leak-through signals are rejected by
a postmixer bandpass filter. The signal Dopplers and the PRN codes are preserved
after the mixing process. Only the carrier frequency is lowered, but the Doppler
remains referenced to the original L-band signal. The A/D conversion process and
automatic gain control (AGC) functions take place at IF. Not shown in the block
diagram are the baseband timing signals that are provided to the digital receiver
channels by the frequency synthesizer phase locked to the reference oscillator's sta-
ble frequency. The IF must be high enough to provide a single-sided bandwidth that
will support the PRN code chipping frequency. An antialiasing IF filter must sup-
press the stopband noise (unwanted out-of-band signals) to levels that are accept-
ably low when this noise is aliased into the GPS signal passband by the A/D
conversion process. The signals from all GPS satellites in view are buried in thermal
noise at IF.
At this point the digitized IF signals are ready to be processed by each of the N
digital receiver channels. No demodulation has taken place, only signal gain and
conditioning plus A/D conversion into the digital IF. Traditionally, these digital
receiver channel functions are implemented in one or more application-specific inte-
grated circuits (ASICs), but SDRs would use field programmable gate arrays
(FPGAs) or even DSPs. This is why these functions are shown as separate from the
receiver processing function in the block diagram of Figure 5.1. The name digital
receiver channel is somewhat misleading since it is neither the ASIC nor FPGA but
the receiver processing function that usually implements numerous essential but
complex (and fortunately less throughput-demanding) baseband functions, such as
the loop discriminators and filters, data demodulation, SNR meters, and phase lock
indicators. The receiver processing function is usually a microprocessor. The micro-
processor not only performs the baseband functions, but also the decision-making
functions associated with controlling the signal preprocessing functions of each digi-
tal receiver channel. It is common that a single high-speed microprocessor supports
the receiver, navigation, and user interface functions.
Figure 5.2 illustrates a high-level block diagram typical of one of the digital
receiver channels where the digitized received IF signal is applied to the input. For
simplification, only the functions associated with the code and carrier tracking loops
are illustrated, and the receiver channel is assumed to be tracking the SV signal in
steady state. Referring to Figure 5.2, first the digital IF is stripped of the carrier (plus
carrier Doppler) by the replica carrier (plus carrier Doppler) signals to produce
in-phase ( I ) and quadraphase ( Q ) sampled data. Note that the replica carrier signal
is being mixed with all of the in-view GPS SV signals (plus noise) at the digital IF.
The I and Q signals at the outputs of the mixers have the desired phase relationships