Reduced Instruction Set Computers (RISCs) - Fundamentals of Computer Organization and Architecture - page 231

10.6.3. SUN UltraSPARC III

The UltraSPARC III is a high-performance superscalar RISC processor that

implements the 64-bit SPARC

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-V9 RISC architecture. There exist a number of
implementations of the SPARC III processor. These include the UltraSPARC IIIi
and the UltraSPARC III Cu. Our coverage in this section will be independent of
any particular implementation. We will however refer to specific implementations
whenever appropriate.
The UltraSPARC III is a third generation 64-bit SPARC

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RISC microprocessor.
It supports a 64-bit virtual address space and a 43-bit physical address space. The
UltraSPARC III employs a multilevel cache architecture. For example, the Ultra-
SPARC IIIi (and the UltraSPARC III Cu) architecture has a 32 KB, four-way set-
associative L1 instruction cache, a 64 KB four-way set-associative L1 data cache,
a 2 KB prefetch cache, and a 2 KB write cache. The UltraSPARC IIIi supports a
1 MB four-way set-associative, unified instruction

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data on chip L2 cache. A
cache block size of 64 bytes is used in the UltraSPARC IIIi. While the UltraSPARC
III Cu architecture supports a 1, 4, or 8 MB two-way set-associative, unified instruc-
tion

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data external cache. Cache block size in the UltraSPARC III Cu varies between
64 bytes (for the 1 MB cache) to 512 bytes (for the 8 MB cache) (Fig. 10.13).
The UltraSPARC III uses two instruction TLBs that can be accessed in parallel
and three data TLBs that can be accessed in parallel. The two instruction TLBs
are organized in a 16-entry fully associative manner to hold entries for 8 KB,
64 KB, 512 KB, and 4 MB page sizes. A 128-entry two-way set-associative TLB
is used exclusively for 8 KB page sizes. The three data TLBs are organized in a
16-entry associative manner for 8 KB, 64 KB, 512 KB, and 4 MB page sizes and
two 512-entry two-way set-associative TLBs that can be programmed to hold any
one page size at a given time. The UltraSPARC III uses a write-allocate, write-
back cache write policy.
The UltraSPARC III pipeline has been covered in Chapter 9 (pages 203-207).
On a final note, it should be mentioned that the UltraSPARC III has been
designed to support a one-to-four way multiprocessing. For this purpose, it uses
the JBus, which supports a small-scale multiprocessor system. The JBus is capable

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Cache L1
(Data 64 KB) +
(Instruction 32 KB) +
(2 KB Prefetch) + (2 Kbyte Write)

Cache L2 (1-8 MB)

Main Memory (up to 16 GB)

Hard Disk (100s of Terabytes)

Figure 10.13 UltraSPARC III memory hierarchy