Reduced Instruction Set Computers (RISCs) - Fundamentals of Computer Organization and Architecture - page 232

UltraSPARC III
Processor

UltraSPARC III
Processor

UltraSPARC III
Processor

UltraSPARC III
Processor

JBUS 128 bit, 200 MHz

Figure 10.14 A four-way UltraSPARC III multiprocessor configuration

of delivering the high bandwidth needed for networking and embedded systems
applications. Through the JBus, processors can attach to a coherent shared bus
with no needed glue logic (Fig. 10.14).

10.7. SUMMARY

A RISC architecture saves the extra chip area used by CISC architectures for decod-
ing and executing complex instructions. The saved chip area is then used to provide
an on-chip instruction cache that can be used to reduce instruction traffic between
the processor and the memory. Common characteristics shared by most RISC
designs are: limited and simple instruction set, large number of general purpose reg-
isters and / or the use of compiler technology to optimize register usage, and optim-
ization of the instruction pipeline. An essential RISC philosophy is to keep the most
frequently accessed operands in registers and minimize register-memory operations.
This can be achieved using one of two approaches: Software Approach, use the com-
piler to maximize register usage by allocating registers to those variables that will be
used the most in a given time period (this is the philosophy used in Stanford MIPs
machine); or Hardware Approach, use more registers so that more variables can be
held in registers for larger periods of time (this is the philosophy used in the Berke-
ley RISC machine). Register windows are multiple small sets of registers, each
assigned to a different procedure. A procedure call automatically switches the
CPU to use a different fixed-size window of registers rather than saving registers
in memory at the call time. At any time, only ONE window of registers is visible
and is addressed as if it were the only set of registers. Window overlapping requires
that temporary registers at one level are physically the same as the parameter regis-
ters at the next level. This overlap allows parameters to be passed without the actual
movement of data.
It is worthwhile mentioning that the classification of processors as entirely pure
RISC or entirely pure CISC is becoming more and more inappropriate and may be
irrelevant. What actually counts is how much performance gain can be achieved by
including an element of a given design style. Most modern processors use a calcu-
lated combination of elements of both design styles. The decisive factor in which
element(s) of each design style to include is made based on a trade-off between