Reduced Instruction Set Computers (RISCs) - Fundamentals of Computer Organization and Architecture - page 230

progress of single-cycle, multiple-cycle, and variable-cycle instructions. Upon the
availability of the functional unit(s) or load data results, the scoreboard unit notifies
all instructions in the queue of the availability of the required register value. Each
queue selects the oldest data-ready and functional-unit-ready instructions for
execution of each cycle. The 21264 integer queue statically assigns instructions to
two of four pipes, either the upper or the lower pipe (Fig. 10.12).
The Alpha 21264 has four integer and two floating-point pipelines. This allows
the processor to dynamically issue up to six instructions in the same cycle. The
issue (or queue) stage maintains an inventory from which it can dynamically
select to issue a maximum of six instructions. There is a 20-entry integer issue
queue and a 15-entry floating-point issue queue. Instruction issue reordering takes
place in the issue stage.
The 21264 uses two integer files, 80-entry each, to store a duplicate of register con-
tents. Two pipes access a single file to form a cluster. The two clusters form a four-
way integer instruction execution. Results are broadcasted from each cluster to the
other cluster. Instructions are dynamically selected by the integer issue queue to exe-
cute on a given instruction pipe. An instruction can heuristically be selected to execute
on the same cluster that produces the result. The 21264 has one 72-entry floating-point
register file. The floating-point register file, together with two instruction execution
pipes, form a cluster. Figure 10.12 shows the register read execution pipes.

On a final note, we should indicate that the 21264 uses a write-invalidate cache
coherence mechanism in the level 2 cache to provide support for shared-memory
multiprocessing. It also supports the following cache states: modified, owned,
shared, exclusive, and invalid.

/

Integer Execution

Integer Register
File (80)

Integer Execution

Cluster

Integer Execution

Integer Register
File (80)

Data
Cache
64 KB
2-way

Integer Execution

Cluster

Floating-point
Multiply
Execution

Floating-point
Register File (72)

Floating-point
Add, Div, SQRT
Execution

C l uster

Figure 10.12 The 21264 execution pipes