Pipelining Design Techniques - Fundamentals of Computer Organization and Architecture - page 203

The prefetch unit operates in the Fetch stage and can fetch 64 bits every cycle from
an instruction-side cache. It can, however, issue one 32-bit instruction per cycle to
the integer unit. Pending instructions are placed in the prefetch buffer by the prefetch
unit. While an instruction is in the prefetch buffer, the branch prediction logic can
decode it to see if it is a predictable branch. The prefetch buffer can hold up to
three instructions and enable the prefetch unit to:

1. Detect branch instructions ahead of the fetch stage
2. Predict those branches that are likely to be taken
3. Remove those branches that are not likely to be taken

If the branch is predicted to be taken, then the instruction address is redirected to
the branch target address. If, however, the branch is predicted not to be taken,
then the next instruction is fetched. In case there is not enough time to completely
remove a branch, the fetch address is redirected anyway, thus reducing branch
penalty.
The integer unit executes unpredictable branches. To quickly obtain the required
address, a dedicated fast branch adder is used. This is done in order to avoid passing
through the barrel shift.
The prefetch buffer is flushed in the following cases:

1. Entry into an exception processing sequence
2. A load to the program counter (PC)
3. An arithmetic manipulation of the PC
4. Execution of an unpredicted branch
5. Detection of an erroneously predicted branch

A taken predicted branch is the only case that does not lead to automatic flush of the
prefetch buffer. Mispredicted branches and unpredicted taken branches lead to a
three-cycle penalty.

9.3.2. UltraSPARC III Processor The UltraSPARC III is based on the SUN

SPARC-V9 RISC architectural specifications. A number of features characterize
the SPARC-V9. Among these are the following:

1. Few and simple instruction formats. All instructions are 32-bit. Memory
access is done exclusively using Load and Store instructions.
2. Few addressing modes. Memory addressing has only two modes,

the

Immediate modes.
3. Triadic register operands. Most instructions operate on two register operands
or one register and a constant operand. The results in both cases are stored in a
third register.
4. Large window register file.

Register þ Register and the Register þ