Pipelining Design Techniques - Fundamentals of Computer Organization and Architecture - page 202

pipeline features of these architectures. The two processors are the ARM 1026EJ-S
and the UltraSPARC III.

9.3.1. ARM 1026EJ-S Processor This processor is part of a family of RISC

processors designed by Advanced RISC Machine (ARM) Company. The series is
designed to suit high-performance, low-cost, and low-power embedded applications.
The ARM 022EJ-S integer core has multiple execution units, thus allowing a number
of instructions to exist in the same pipeline stage. It also allows the execution of sim-
ultaneous instructions. The ARM 1026EJ-S can deliver a peak throughput of one
instruction per cycle. The integer core consists of the following units:

1. Prefetch unit: This unit is responsible for instruction fetch. It also predicts the
outcome of branches whenever possible.
2. Integer unit: This unit is responsible for decoding of instructions coming out
of the prefetch unit. This unit contains a barrel shifter, ALU, and a multiplier.
It executes instructions such as MOV, ADD, and MUL. The integer unit helps
the load store unit to execute load and store instructions. It also helps in

executing some coprocessor instructions.
3. Load

/

/ Store unit: This unit can load or store two registers (64 bits) per cycle.

ARM 1022EJ-S is a pipeline processor whose ALU consists of six stages. These are:

1. Fetch stage: for instruction cache access and branch prediction for instructions
that have already been fetched.
2. Issue stage: for initial instruction decoding.
3. Decode stage: for final instruction decode, register read for ALU operations,
forwarding, and initial interlock resolution.
4. Execute stage: for data access address calculation, data processing shift, shift
and saturate, ALU operations, first stage multiplication, flag setting, condition
code check, branch mispredict detection, and store data register read.
5. Memory stage: for data cache access, second stage multiplication, and
saturations.
6. Write stage: for register write and instruction retirement.

In this arrangement, the Fetch stage uses a first-in-first-out (FIFO) buffer that can
hold up to three instructions. The Issue and Decode stages can contain a predicted
branch in parallel with one other instruction. The Execute, Memory, and Write
stages can simultaneously contain any of the following.

1. A predicted branch
2. An ALU or multiply instruction
3. Ongoing multiply load or store multiple instructions
4. Ongoing multicycle coprocessor instructions