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When it recognizes such data dependency, a “smart” compiler can replace the above
sequence by the following sequence:
Store R
2
,(R
3
);
M[R
3
]
R
2
Move R
2
, R
4
;
R
4
R
2
FETCH-FETCH
This case represents data dependency in which the data stored by an
instruction is also needed as an operand by a subsequent instruction. Consider the
following instruction sequence:
Load
(R
3
), R
2
;
R
2
M[R
3
]
Load
(R
3
), R
4
;
R
4
M[R
3
]
In this sequence, the operand needed by the first instruction (the contents of memory
location whose address is stored in register R
3
) is also needed as an operand for the
second instruction. Therefore, this operand can be immediately (forwarded) moved
into register R
4
. When it recognizes such data dependency, a “smart” compiler can
replace the above sequence by the following sequence.
Load
(R
3
), R
2
;
R
2
M[R
3
]
Move R
2
, R
4
;
R
4
R
2
STORE-STORE
This is the case in which the data stored by an instruction is overwrit-
ten by a subsequent instruction. Consider the following instruction sequence:
Store R
2
,(R
3
);
M[R
3
]
R
2
Store R
4
,(R
3
);
M[R
3
]
R
4
In this sequence, the results written during the first instruction (the content of
register R
2
is written into memory location whose address is stored in register R
3
)
is overwritten during the second instruction by the contents of register R
4
. Assuming
that these two instructions are executed in sequence and that the result written by the
first instruction will not be needed by an I
O operation, for example, a DMA, then
the sequence of these two instructions can be replaced by the following single
instruction.
/
Store R
4
,(R
3
);
M[R
3
]
R
4
9.3. EXAMPLE PIPELINE PROCESSORS
In this section, we briefly present two pipeline processors that use a variety of the
pipeline techniques presented in this chapter. Our focus in this coverage is on the
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