Pipelining Design Techniques - Fundamentals of Computer Organization and Architecture - page 204

Instruction Issue Unit (IIU)

Instruction Cache

Instruction Queue
Steering Logic

Integer Execution Unit (IEU) Floating-Point Unit (FPU)

FP Register File Add/Subtract

Integer Register File Dependency/Trap

Multiply

ALU Pipe

Divide

Load/Store/Special

Graphics unit

Data Cache Unit (DCU)

Data Write Store

Prefetch

System Interface Unit (SIU) External Memory Unit

Snoop Pipe Controller Data Switch Controller SRAM Eternal Cache Tags DRAM

Figure 9.16 The functional units of the UltraSPARC III

The UltraSPARC III processor uses six independent units (see Fig. 9.16).
These are:

1. The Instruction Issue Unit (IIU). This unit predicts the program flows, fetches
the predicted path from memory and directs the fetched instructions to the
execution pipeline. Instructions are forwarded to either the IEU or the FPU.
The IIU incorporates a four-way associative instruction cache, an address
translation buffer, and a 16K-entry branch predictor.
2. The Integer Execute Unit (IEU). This unit executes all integer instructions,
including the integer loading and storing, the integer arithmetic, the logic,
and the branch instructions. The IEU is capable of executing up to four integer
instructions concurrently during a cycle time.