Input–Output Design and Organization - Fundamentals of Computer Organization and Architecture - page 176

DMA Request

DMA Acknowledgement

DMA
Controller

CPU

Address Bus

Data Bus

Device Memory

Control Signals

Figure 8.10 DMA controller shares the CPU's memory bus

Direct memory access controllers require initialization by the CPU. Typical setup
parameters include the address of the source area, the address of the destination area,
the length of the block, and whether the DMA controller should generate a processor
interrupt once the block transfer is complete. A DMA controller has an address reg-
ister, a word count register, and a control register. The address register contains an
address that specifies the memory location of the data to be transferred. It is typically
possible to have the DMA controller automatically increment the address register
after each word transfer, so that the next transfer will be from the next memory
location. The word count register holds the number of words to be transferred.
The word count is decremented by one after each word transfer. The control register
specifies the transfer mode.
Direct memory access data transfer can be performed in burst mode or single-
cycle mode. In burst mode, the DMA controller keeps control of the bus until all
the data has been transferred to (from) memory from (to) the peripheral device.
This mode of transfer is needed for fast devices where data transfer cannot be
stopped until the entire transfer is done. In single-cycle mode (cycle stealing), the
DMA controller relinquishes the bus after each transfer of one data word. This mini-
mizes the amount of time that the DMA controller keeps the CPU from controlling
the bus, but it requires that the bus request acknowledge sequence be performed for

every single transfer. This overhead can result in a degradation of the performance.
The single-cycle mode is preferred if the system cannot tolerate more than a few
cycles of added interrupt latency or if the peripheral devices can buffer very large
amounts of data, causing the DMA controller to tie up the bus for an excessive
amount of time.
The following steps summarize the DMA operations:

/

1. DMA controller initiates data transfer.
2. Data is moved (increasing the address in memory, and reducing the count of
words to be moved).