Input–Output Design and Organization - Fundamentals of Computer Organization and Architecture - page 175

INTTYPEH and INTTYPEL registers. Each bit in these registers corresponds to an
interrupt source available in the system. Setting a bit will select its corresponding
interrupt source as a Fast interrupt, whereas clearing this bit will select its corre-
sponding bit as a Normal interrupt. In the INTTYPEL register, bit 0 corresponds
to interrupt source 0, bit 1 corresponds to interrupt source 1, and so on up to bit
31, which corresponds to interrupt source 31. In the INTTYPEH register, bit 0 cor-
responds to interrupt source 32, bit 1 corresponds to interrupt source 33, and so on up
to bit 31, which corresponds to interrupt source 63.
After determining the type of the pending interrupt, the next step is to enable the
interrupt. This can be done via the INTENABLEH and INTENABLEL registers. To
enable a pending interrupt to the core, its corresponding interrupt source bit in the
INTENABLEH or INTENABLEL must be set. Likewise, to disable the interrupt,
clear this bit. In the INTENABLEL register, bit 0 corresponds to interrupt source
0, bit 1 corresponds to interrupt source 1, and so on up to bit 31, which corresponds
to interrupt source 31. In the INTENABLEH register, bit 0 corresponds to interrupt
source 32, bit 1 corresponds to interrupt source 33, and so on up to bit 31, which
corresponds to interrupt source 63. For example, to select interrupt source bit 15
as a Normal interrupt, clear bit 15 in the INTTYPEL register. Then, to enable this
interrupt, set bit 15 in the INTENABLEL register. Likewise, to select interrupt
source bit 45 as a Fast interrupt, set bit 13 in the INTTYPEH register. Then, to
enable this interrupt, set bit 13 in the INTENABLEH. The AITC also allows the pro-
grammer to prioritize the pending Normal interrupt sources to one of 16 different
priority levels. This can be done in the NIPRIORITY[7:0] registers.
8.4. DIRECT MEMORY ACCESS (DMA)
The main idea of direct memory access (DMA) is to enable peripheral devices to cut
out the “middle man” role of the CPU in data transfer. It allows peripheral devices to
transfer data directly from and to memory without the intervention of the CPU. Having
peripheral devices access memory directly would allow the CPU to do other work,
which would lead to improved performance, especially in the cases of large transfers.
The DMA controller is a piece of hardware that controls one or more peripheral
devices. It allows devices to transfer data to or from the system's memory without
the help of the processor. In a typical DMA transfer, some event notifies the DMA
controller that data needs to be transferred to or from memory. Both the DMA and
CPU use memory bus and only one or the other can use the memory at the same
time. The DMA controller then sends a request to the CPU asking its permission
to use the bus. The CPU returns an acknowledgment to the DMA controller granting
it bus access. The DMA can now take control of the bus to independently conduct
memory transfer. When the transfer is complete the DMA relinquishes its control of
the bus to the CPU. Processors that support DMA provide one or more input signals
that the bus requester can assert to gain control of the bus and one or more output
signals that the CPU asserts to indicate it has relinquished the bus. Figure 8.10
shows how the DMA controller shares the CPU's memory bus.