Input–Output Design and Organization - Fundamentals of Computer Organization and Architecture - page 177

3. When word count reaches zero, the DMA informs the CPU of the termination
by means of an interrupt.
4. The CPU regains access to the memory bus.

A DMA controller may have multiple channels. Each channel has associated with it
an address register and a count register. To initiate a data transfer the device driver
sets up the DMA channel's address and count registers together with the direction of
the data transfer, read or write. While the transfer is taking place, the CPU is free to
do other things. When the transfer is complete, the CPU is interrupted.
Direct memory access channels cannot be shared between device drivers. A
device driver must be able to determine which DMA channel to use. Some devices
have a fixed DMA channel, while others are more flexible, where the device driver
can simply pick a free DMA channel to use.
Linux tracks the usage of the DMA channels using a vector of dma_chan data
structures (one per DMA channel). The dma_chan data structure contains just two
fields, a pointer to a string describing the owner of the DMA channel and a flag indi-
cating if the DMA channel is allocated or not.

8.5. BUSES

A bus in computer terminology represents a physical connection used to carry a
signal from one point to another. The signal carried by a bus may represent address,
data, control signal, or power. Typically, a bus consists of a number of connections
running together. Each connection is called a bus line. A bus line is normally ident-
ified by a number. Related groups of bus lines are usually identified by a name. For
example, the group of bus lines 1 to 16 in a given computer system may be used to
carry the address of memory locations, and therefore are identified as address lines.
Depending on the signal carried, there exist at least four types of buses: address,
data, control, and power buses. Data buses carry data, control buses carry control
signals, and power buses carry the power-supply

ground voltage. The size
(number of lines) of the address, data, and control bus varies from one system to
another. Consider, for example, the bus connecting a CPU and memory in a given
system, called the CPU bus. The size of the memory in that system is 512M-
word and each word is 32 bits. In such system, the size of the address bus should
be log 2 (512

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2 20 )

29 lines, the size of the data bus should be 32 lines, and at
least one control line (

¼

R = W) should exist in that system.
In addition to carrying control signals, a control bus can carry timing signals.
These are signals used to determine the exact timing for data transfer to and from
a bus; that is, they determine when a given computer system component, such as
the processor, memory, or I

O devices, can place data on the bus and when they
can receive data from the bus. A bus can be synchronous if data transfer over the
bus is controlled by a bus clock. The clock acts as the timing reference for all bus
signals. A bus is asynchronous if data transfer over the bus is based on the avail-
ability of the data and not on a clock signal. Data is transferred over an asynchronous

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