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In-Depth Information
TABLE 6.4 Fully Associative Mapping
MM
block
number
(i)
Cache
block
number
Cache status
Cache
hit
/
miss
Request
BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7
A(0,0)
Miss
0
0
0 1
00
A(0,1)
Miss
2
1 0101
0011
A(0,2)
Miss
4
2 010101
001122
A(0,3)
Miss
6
3 01010101
00112233
A(0,4)
Miss
8
4 0101010101
0011223344
A(0,5)
Miss
10
5 010101010101
001122334455
A(0,6)
Miss
12
6 01010101010101
00112233445566
A(0,7)
Miss
14
7 0101010101010101
0011223344556677
A(1,0)
Hit
0
0 0101010101010101
0011223344556677
A(1,1)
Hit
2
1 0101010101010101
0011223344556677
A(1,2)
Hit
4
2 0101010101010101
0011223344556677
A(1,3)
Hit
6
3 0101010101010101
0011223344556677
A(1,4)
Hit
8
4 0101010101010101
0011223344556677
A(1,5)
Hit
10
5 0101010101010101
0011223344556677
A(1,6)
Hit
12
6 0101010101010101
0011223344556677
A(1,7)
Hit
14
7 0101010101010101
0011223344556677
can be maintained between cache words and their counterparts in the main memory.
In the following paragraphs, we discuss these write policies. In particular, we dis-
cuss two main cases: cache write policies upon a cache hit and the cache write pol-
icies upon a cache miss. We also discuss the cache read policy upon a cache miss.
Cache read upon a cache hit is straightforward.
Cache Write Policies Upon a Cache Hit
There are essentially two possible
write policies upon a cache hit. These are the write-through and the write-back.
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