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TABLE 6.3 Direct Mapping
MM
block
number
(i)
Cache
block
number
(j)
Cache status
Cache
hit / miss
Request
BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7
A(0,0)
Miss
0
0
0 1
00
A(0,1)
Miss
2
2
0 1
0 1
00
11
A(0,2)
Miss
4
4
0 1
0 1
0 1
00
11
22
A(0,3)
Miss
6
6
0 1
0 1
0 1
0 1
00
11
22
33
A(0,4)
Miss
8
0
0
1
0 1
0 1
0 1
44
11
22
33
A(0,5)
Miss
10
2
0 1
0
1
0 1
0 1
44
55
22
33
A(0,6)
Miss
12
4
0 1
0 1
0
1
0 1
44
55
66
33
A(0,7)
Miss
14
6
0 1
0 1
0 1
0
1
44
55
66
77
A(1,0)
Miss
0
0
0
1
0 1
0 1
0 1
00
55
66
77
A(1,1)
Miss
2
2
0 1
0
1
0 1
0 1
00
11
66
66
A(1,2)
Miss
4
4
0 1
0 1
0
1
0 1
00
11
22
66
A(1,3)
Miss
6
6
0 1
0 1
0 1
0
1
00
11
22
33
A(1,4)
Miss
8
0
0
1
0 1
0 1
0 1
44
11
22
33
A(1,5)
Miss
10
2
0 1
0
1
0 1
0 1
44
55
22
33
A(1,6)
Miss
12
4
0 1
0 1
0
1
0 1
44
55
66
33
A(1,7)
Miss
14
6
0 1
0 1
0 1
0
1
44
55
66
77
6.2.7. Cache Write Policies
Having discussed the main issues related to cache mapping techniques and the repla-
cement policies, we would like to address a very important related issue, that is,
cache coherence. Coherence between a cache word and its copy in the main
memory should be maintained at all times, if at all possible. A number of policies
(techniques) are used in performing write operations to the main memory blocks
while residing in the cache. These policies determine the degree of coherence that
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