Memory System Design I - Fundamentals of Computer Organization and Architecture - page 126

TABLE 6.5 Set-Associative Mapping

Cache status

MM
block
number
(i)

Cache
block
number

Set # 0 Set # 1 Set # 2 Set # 3

Cache
hit / miss Request BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7

A(0,0) Miss 0 0 0 1

00

A(0,1) Miss 2 2 0 1 0 1

00 11

A(0,2) Miss 4 0 0101 01

0022 11

A(0,3) Miss 6 2 0101 0101

0022 1133

A(0,4) Miss 8 0 0 1 0 1 0101

4422 1133

A(0,5) Miss 10 2 0101 0101

4422 5533

A(0,6) Miss 12 0 0 1 0 1 0101

4466 5533

A(0,7) Miss 14 2 0101 0101

4466 5577

A(1,0) Miss 0 0 0 1 0 1 0101

0066 5577

A(1,1) Miss 2 2 0101 0101

0066 1177

A(1,2) Miss 4 0 0 1 0 1 0101

0022 1177

A(1,3) Miss 6 2 0101 0101

0022 1133

A(1,4) Miss 8 0 0 1 0 1 0101

4422 1133

A(1,5) Miss 10 2 0101 0101

4422 5533

A(1,6) Miss 12 0 0 1 0 1 0101

4466 5533

A(1,7) Miss 14 2 0101 0101

4466 4422

In the write-through policy, every write operation to the cache is repeated to the
main memory at the same time. In the write-back policy, all writes are made to
the cache. A write to the main memory is postponed until a replacement is
needed. Every cache block is assigned a bit, called the dirty bit, to indicate that at
least one write operation has been made to the block while residing in the cache.
At replacement time, the dirty bit is checked; if it is set, then the block is written
back to the main memory, otherwise, it is simply overwritten by the incoming