Information Technology Reference
In-Depth Information
References
1. Caldwell, A.E., Kahng, A.B., Markov, I.L.: Can recursive bisection alone pro-
duce routable, placements? In: Proceedings of Design Automation Conference, pp.
477-482 (2000)
2. Wang, M., Yang, X., Sarrafzadeh, M.: Dragon2000: standard-cell placement tool
for large industry circuits. In: Proceedings of IEEE/ACM International Conference
on Computer Aided Design (ICCAD), pp. 260-263 (2000)
3. Agnihotri, A., Yildiz, M.C., Khatkhate, A., Mathur, A., Ono, S., Madden, P.H.:
Fractional cut: improved recursive bisection placement. In: Proceedings of Interna-
tional Conference on Computer Aided Design (ICCAD), pp. 307-310 (November
2003)
4. Sechen, C., Sangiovanni-Vincentelli, A.: The timberwolf placement and routing
package. IEEE Journal of Solid-State Circuits 20(2), 510-522 (1985)
5. Kahng, A.B., Wang, Q.: Implementation and extensibility of an analytic placer.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Sys-
tems 24(5), 734-747 (2005)
6. Cong, J., Xie, M.: A robust detailed placement for mixed-size ic designs. In: Pro-
ceedings of Asia and South Pacific Conference on Design Automation, pp. 188-194
(January 2006)
7. Shahookar, K., Mazumder, P.: VLSI cell placement techniques. ACM Computing
Surveys 23(2), 143-220 (1991)
8. Chang, C.C., Cong, J., Romesis, M., Xie, M.: Optimality and scalability study of
existing placement algorithms. IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems 23(4), 537-549 (2004)
9. Alpert, C.J., Caldwell, A.E., Kahng, A.B., Markov, I.L.: Hypergraph partitioning
with fixed vertices (VLSI CAD). IEEE Transactions on Computer-Aided Design
of Integrated Circuits and Systems 19(2), 267-272 (2000)
10. Selvakkumaran, N., Karypis, G.: Theto - a fast and high-quality partitioning driven
global placer. Technical report, in university of minnesota - computer science and
engineering technical reports (2003)
11. Chen, T.C., Hsu, T.C., Jiang, Z.W., Chang, Y.W.: Ntuplace: a ratio partitioning
based placement algorithm for large-scale mixed-size designs. In: Proceedings of
the 2005 International Symposium on Physical Design, ISPD 2005, pp. 236-238.
ACM, New York (2005)
12. Capo: Tool,
http://vlsicad.eecs.umich.edu/BK/PDtools/tar.gz/Placement-bin/
(accessed 17 January 2013)
13. Karypis, G., Kumar, V.: Multilevel k-way hypergraph partitioning. In: Proceedings
of 36th Design Automation Conference, pp. 343-348 (1999)
14. Kennings, A., Markov, I.: Analytical minimization of half-perimeter wirelength.
In: Proceedings of Design Automation Conference (ASP-DAC), pp. 179-184 (June
2000)
15. Yang, X., Choi, B.K., Sarrafzadeh, M.: A standard-cell placement tool for designs
with high row utilization. In: Proceedings of the 2002 IEEE International Confer-
ence on Computer Design: VLSI in Computers and Processors, pp. 45-47 (2002)
 
 
Search WWH ::




Custom Search