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Preemptive Test Scheduling
for Network-on-Chip Using Particle
Swarm Optimization
Kanchan Manna 1 , Shailesh Singh 2 ,
Santanu Chattopadhyay 3 , and Indranil Sengupta 4
1 School of Information Technology
2 , 3 Dept. of Electronics and Elec. Comm. Engg.
4 Dept. of Computer Science
Indian Institute of Technology Kharagpur, India - 721 302
{ kanchanm@sit,santanu@ece,isg@cse } .iitkgp.ernet.in,
shailesh17.singh@gmail.com
Abstract. Network-on-Chip (NoC) has evolved as a promising tech-
nique for the present-day's communication in the VLSI design paradigm.
It ensures reusability, parallelism and scalability. To reduce the testing
cost of such a system, the existing communication structure ca be reused.
In this paper, we have proposed a Particle Swarm Optimization (PSO)
based mixed test scheduling approach to test the cores in the NoC envi-
ronment. It incorporates both non-preemptive and preemptive tests. Ex-
perimental results for ITC'02 System-on-Chip (SoC) benchmarks show
that the PSO based mixed test scheduling approach eciently reduces
the overall test application time compared to other existing works.
Keywords: NoC testing, PSO, Non-preemptive testing and preemptive
testing.
1 Introduction
Network-on-Chip (NoC) has evolved as a very promising methodology to imple-
ment core based systems, in which, a number of simple routers are interconnected
following some topology (most commonly, mesh). The cores are attached to the
routers. Electrical signal exchanges between the cores are replaced by message
passing via the router network. Such an environment, though well suited for
the VLSI design paradigm based on reuse of IP-cores, testing becomes a major
challenge. Since the input-output lines of all IP-cores are not available at system
input-output pins, a major task is to transport the test patterns from system
input to the inputs of individual IP cores, collect their responses and transfer to
the system output. Moreover, to reduce system-level pin count and area over-
head, it is advisable to use the on-chip network itself for test data transportation.
This work is partially supported by Department of Information and Technology,
Govt. of India (9(5)/2010-MDD), Dated 23/11/2011.
 
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